Hendrik F. Hamann

Active control of slow light on a chip with photonic crystal waveguides

It is known that light can be slowed down in dispersive materials near resonances. Dramatic reduction of the light group velocity—and even bringing light pulses to a complete halt—has been demonstrated recently in various atomic and solid state systems, where the material absorption is cancelled via quantum optical coherent effects. Exploitation of slow light phenomena has potential for applications ranging from all-optical storage to all-optical switching. Existing schemes, however, are restricted to the narrow frequency range of the material resonance, which limits the operation frequency, maximum data rate and storage capacity. Moreover, the implementation of external lasers, low pressures and/or low temperatures prevents miniaturization and hinders practical applications. Here we experimentally demonstrate an over 300-fold reduction of the group velocity on a silicon chip via an ultra-compact photonic integrated circuit using low-loss silicon photonic crystal waveguides that can support an optical mode with a submicrometre cross-section. In addition, we show fast (∼100 ns) and efficient (2 mW electric power) active control of the group velocity by localized heating of the photonic crystal waveguide with an integrated micro-heater.

Thermal-aware task scheduling at the system software level

Power-related issues have become important considerations in current generation microprocessor design. One of these issues is that of elevated on-chip temperatures. This has an adverse effect on cooling cost and, if not addressed suitably, on chip reliability. In this paper we investigate the general trade-offs between temporal and spatial hot spot mitigation schemes and thermal time constants, workload variations and microprocessor power distributions. By leveraging spatial and temporal heat slacks, our schemes enable lowering of on-chip unit temperatures by changing the workload in a timely manner with Operating System(OS) and existing hardware support.

Strength of the electric field in apertureless near-field optical microscopy

Enhancement γ of the electrical field at the end of a tip relative to the incident field in a focused radiation beam is calculated by the finite-element time-domain (FETD) method. First, the reliability of the FETD method is established by calculating the electric field on simple structures like thin cylinders, spheres, and ellipsoids, and comparing the results with analytical solutions. The calculations on these test structures also reveal that phase retardation effects substantially modify γ when the size of the structure is larger than approximately λ/4, λ being the radiation wavelength. For plasmon resonance, in particular, phase retardation severely reduces the resonance and the expected field enhancement for a gold tip. The small value of γ=4 calculated by FETD is about an order of magnitude smaller than the value found in recent published work. Resonance effects can be recovered for special tips, which have a discontinuity or a different material composition at the end of the tip. Some tuning of th...

Hotspot-Limited Microprocessors: Direct Temperature and Power Distribution Measurements

An experimental technique is presented, which allows for spatially-resolved imaging of microprocessor power (SIMP). In a first step this method utilizes infrared (IR) thermal imaging, while the processor is effectively cooled using an IR-transparent heat sink. In the second step the underlying power distribution is derived by determining the temperature fields for each individual power source on the chip. The measured chip temperature distribution is represented as a superposition of these temperature fields. The SIMP data reveals significant temporal and spatial variations of the microprocessor power/temperature distribution, which can be attributed to the circuit layout as well as to the varying utilization levels across the processor while running full workloads. In this paper we have applied the SIMP method to the dual core PowerPCtrade970MP microprocessor to measure detailed temperature and power distributions under full operating conditions. In the first part of the paper the impact of power and temperature limitations of high performance CMOS chips is discussed in detail, where we distinguish between hotspot-limited (or temperature-limited) and power-limited chips. The discussion shows the importance of temperature and power distributions for chip floor planning, layout, design and architecture. Second, we present the experimental details of the SIMP method, which is applied to the dual core PowerPC970MP to directly measure the temperature and power fields as a function of workload and frequency. A pronounced movement of the hotspot location is observed. Finally, the hotspot of a competitive microprocessor is compared by measuring temperature efficiencies (temperature increase/performance) for the same workloads and cooling conditions

TAPO: Thermal-aware power optimization techniques for servers and data centers

A large portion of the power consumption of data centers can be attributed to cooling. In dynamic thermal management mechanisms for data centers and servers, thermal setpoints are typically chosen statically and conservatively, which leaves significant room for improvement in the form of improved energy efficiency. In this paper, we propose two hierarchical thermal-aware power optimization techniques that are complementary to each other and achieve (i) lower overall system power with no performance penalty or (ii) higher performance within the same power budget.

Uncovering energy-efficiency opportunities in data centers

The combination of rapidly increasing energy use of data centers (DCs), which is triggered by dramatic increases in IT (information technology) demands, and increases in energy costs and limited energy supplies has made the energy efficiency of DCs a central concern from both a cost and a sustainability perspective. This paper describes three important technology components that address the energy consumption in DCs. First, we present a mobile measurement technology (MMT) for optimizing the space and energy efficiency of DCs. The technology encompasses the interworking of an advanced metrology technique for rapid data collection at high spatial resolution and measurement-driven modeling techniques, enabling optimal adjustments of a DC environment within a target thermal envelope. Specific example data demonstrating the effectiveness of MMT is shown. Second, the static MMT measurements obtained at high spatial resolution are complemented by and integrated with a real-time sensor network. The requirements and suitable architectures for wired and wireless sensor solutions are discussed. Third, an energy and thermal model analysis for a DC is presented that exploits both the high-spatial-resolution (but static) MMT data and the high-timeresolved (but sparse) sensor data. The combination of these two data types (static and dynamic), in conjunction with innovative modeling techniques, provides the basis for extending the MMT concept toward an interactive energy management solution.

Spatially-resolved imaging of microprocessor power (SIMP): hotspots in microprocessors

In this paper we present the details of a new technique, which allows for spatially-resolved imaging of microprocessor power (SIMP) under full operational conditions. The method involves two steps: In the first step it utilizes infra-red (IR) thermal imaging, while an IR-transparent coolant flows through a specially designed cooling cell directly over the microprocessor. In the second step the underlying power distribution is derived by determining the temperature fields for each individual power source on the chip. The measured chip temperature distribution is then represented as a superposition of these temperature fields. The SIMP data reveals significant temporal and spatial variations of the microprocessor power/temperature distribution, which can be attributed to the circuit layout as well as to the varying utilization levels across the processor while running real workloads. More specifically, strong non-uniformities or hotspots in the microprocessor power distributions are observed, which have significant implications for packaging and cooling designs

Thermally assisted recording beyond traditional limits

This work demonstrates that current magnetic storage density limitations due to superparamagnetic effects can be overcome by thermally assisted writing. Specifically, we write magnetization patterns on thin magnetic films that correspond to storage densities of ∼400 Gbit/in.2. Simple thermal diffusion considerations predict potential storage densities of >1 Tbit/in.2 accompanied by recording speeds of >1 GHz.

Methods and techniques for measuring and improving data center best practices

Here we present a novel, measurement-based method for characterizing and improving the energy efficiency of a data center (DC). The technique not only yields a clear set of measurement-based best practices metrics, but also provides clear guidance to a DC manager to substantially improve the DC energy efficiency. We describe a technology which exploits the superiority of fast and massive parallel data collection using the Mobile Measurement Technology (MMT) [1] to drive towards quantitative, measurement-driven DC best practices implementation. A large representative raised-floor DC is mapped by the MMT methodology readily yielding the DC layout, very detailed 3D temperature distributions, flows and other relevant physical parameters of the specific facility. The data is used to calculate key metrics (horizontal and vertical hotspots, targeted air flow, plenum temperature, air conditioning unit utilization and flow levels). These metrics provide insights into the sources of energy inefficiencies of the current DC setup, and systematically guide DC managers to improve various best practice aspects in the specific DC. It is shown that significant energy reductions can be achieved utilizing the above described best practices methodology.

Silicon nanowire piezoresistance: Impact of surface crystallographic orientation

We investigate piezoresistance in lithographically defined silicon nanowires of various cross-sectional aspect ratios. Both ⟨110⟩- and ⟨100⟩-oriented nanowires are investigated under ⟨110⟩-oriented strain. The nanowire thickness is varied from 23 to 45 nm and the nanowire width is varied from 5 to 113 nm. Our data shows piezoresistance in silicon nanowires being a surface induced effect with {110} surfaces inducing a much larger piezoresistance than {100} surfaces. This is consistent with a higher density of surface states on {110} surfaces than on {100} surfaces. Our experimental findings support recent computational work pointing toward surface states being the source of giant piezoresistance in silicon nanowires.