Hendrik Seidel

Synchronous Transfer Architecture (STA)

This paper presents a novel micro-architecture for high-performance and low-power DSPs. The underlying Synchronous Transfer Architecture (STA) fills the gap between SIMD-DSPs and coarse-grain reconfigurable hardware. STA processors are modeled using a common machine description suitable for both compiler and core generator. The core generator is able to generate models in Lisa, System-C, and VHDL. A special emphasis is placed on the good synthesis of the generated VHDL model.

Implementation of recursive digital filters into vector SIMD DSP architectures

Recently, digital signal processors featuring vector SIMD instructions have gained renewed attention, since they offer the potential to speed up the computation of digital signal processing algorithms. However, when implementing recursive algorithms the maximum achievable speed-up factors are upper bounded. In this paper, we investigate these performance limitations when pure recursive filters are implemented into parallel DSP architectures. We show that by applying algebraic transformations a block formulation of any recursive filter can be derived, which can be efficiently implemented into SIMD DSP architectures. We also show that the number of additional vector operations introduced by the transformation grows linearly with the level of parallelism and that it does not depend on the recursion order. These results enable the achievement of important speed-up factors even for low order recursions. Moreover, we introduce a suitable algebraic notation of the block formulation of the recursive filter, which reveals the processor instructions required to implement the algorithm into the SIMD DSP.

A GFLOPS Vector-DSP for Broadband Wireless Applications

In this paper the low-power high-performance floating-point vector DSP (SAMIRA) is presented primarily intended for base-band signal processing applications. SAMIRA DSP is build upon 0.13mum UMC technology running at a maximum clock frequency of 212MHz. The processor combines SIMD and VLIW parallelism and it represents the first silicon prototype based on synchronous transfer micro-architecture (STA). The implementation results demonstrate the quantitative performance of the processor

Compiler Scheduling for STA-Processors

This paper presents an adaptation of the list scheduling algorithm to generate code for processors of the Synchronous Transfer Architecture (STA) by applying techniques known from RISC and TTA. The proposed scheduling approach is based on informed, deterministic algorithms that can be implemented run-time efficiently. Although the presented compiler prototype does not generate optimized code, it provides a proof-of-concept of the feasibility of the proposed compiler architecture.

Implementing a receiver for terrestrial digital video broadcasting in software on an application-specific DSP

Terrestrial digital video broadcasting (DVB-T) is currently being introduced in many European countries and planned to supplement or replace current analogue broadcasting schemes in a large part of the world. It is also considered as an additional downlink medium for third generation UMTS mobile telephones, where a special variant, DVB-H, is under development. Current DVB-T receivers still are built upon dedicated application specific integrated circuits (ASIC). However, designing ASIC is a tedious and expensive task. We show that it is possible to implement a DVB-T receiver in software on an application-specific digital signal processor (AS-DSP). We analyze the computational requirements of a DVB-T receiver and investigate its potential for parallelization. Further, we present our AS-DSP, the M5-DSP, which is based on a novel architecture and design methodology, and report on implementing the core algorithms of a DVB-T receiver on it.

Energy efficiency vs. programmability trade-off: architectures and design principles

Performance achievements on programmable architectures due to process technology are reaching their limits, since designs are becoming wire- and power-limited rather than device limited. Likewise, traditional exploitation of instruction level parallelism saturates as the conventional approach for designing wider issue machines leads to very expensive interconnections, big instruction memory footprint and high register file pressure. New architectural concepts targeted to the application domain of media processing are needed in order to push current state-of-the-art limitations. To this end, we regard media applications as a collection of tasks which consume and produce chunks of data. The exploitation of task level parallelism as well as more traditional forms of parallelism is a key issue for achieving the required amount of MOPS/Watt and MOPS/mm2 for media applications. Tasks comprise data transfers and number crunching algorithm kernels, which are very computing-intensive yet highly predictable. Moreover, most of the data manipulated by a task is of a local nature. Granularity and characteristics of these tasks will lead us in this paper to draw conclusions about memory hierarchy, task scheduling strategies and efficient low-overhead programmable architectures for highly predictable kernel computations

Generated DSP Cores for Implementation of an OFDM Communication System

Application tailored signal processors fill the gap between ASICs and general purpose DSPs. Single Instruction Multiple Data(SIMD) Signal Processors offer high computational power with low control overhead. This paper describes the development of a multi-processor OFDM-System x using automatically generated SIMD-DSP Cores. The focus of this case of study was the test of our integrated design flow which is based on our core generation tool. We show how with our design methodology we reduce the design cycle in comparsion with other HW/SW Co-design tools and traditional design flows.

Hardware/software co-design of a SIMD-DSP-based DVB-T receiver

The demand for increasing design complexity has to face decreasing design time and design cost issues. Traditional full custom design flows are not reasonable to cope with these challenges. We have developed a design exploration platform, which provides access to main chip design parameters beginning from early design stages. With this platform, architecture and hardware/software partitioning failures are correctable with low change cost in a short time. Our designs are based on synchronous transfer architecture SIMD DSP cores with a tailored instruction set. Automatic core generation tools speed up the design and verification process. In this paper we present our design exploration platform and a use case study for a DVB-T/H like OFDM-receiver and transmitter build with our design methodology.

Automatic Code Generation for SIMD DSP Architectures: An Algebraic Approach

Driven by the ever increasing algorithm complexity on the field of mobile communications systems, SIMD DSP architectures have emerged as an approach that offers the necessary processing power at reasonable levels of die size and power consumption. However, this kind of DSP architectures imposes new challenges for programmers, since algorithms have to be designed to exploit the available parallelism on the processor. Taking as a starting point an algebraic framework that captures the SIMD computational model, we report in this paper about our efforts to design and automatically generate object code for our family of DSP architectures independent of the available SIMD parallelism. We show how these algebraic structures can be used as a high level programming language that offers a unified approach to design and describe algorithms using SIMD parallelism. Moreover, we show how these algebraic structures offer concise rules for the automatic code generation.

Design and automatic code generation of the LMS algorithm for SIMD signal processors

Taking as a starting point a collection of algebraic primitives that captures the SIMD computational model, we show in this paper our methodology for designing, mapping and implementing algorithms for SIMD-vector signal processors with scalable level of parallelism. Taking as an example the LMS, we show how an algorithm, which has been designed to exhibit a suitable level of data parallelism, can be described by these algebraic primitives. In turn, these algebraic primitives are programmed in a matrix oriented language. A suitable compiler generates object code for SIMD processors with a scalable number of processing elements.