Heon-Bok Lee

A normally off GaN n-MOSFET with Schottky-barrier source and drain on a Si-auto-doped p-GaN/Si

We have fabricated an enhancement-mode n-channel Schottky-barrier-MOSFET (SB-MOSFET) for the first time on a high mobility p-type GaN film grown on silicon substrate. The metal contacts were formed by depositing Al for source/drain contact and Au for gate contact, respectively. Fabricated SB-MOSFET exhibited a threshold voltage of 1.65 V, and a maximum transconductance(g/sub m/) of 1.6 mS/mm at V/sub DS/=5V, which belongs to one of the highest value in GaN MOSFET. The maximum drain current was higher than 3 mA/mm and the off-state drain current was as low as 3 nA/mm.

Formation of Low-Resistivity Nickel Silicide with High Temperature Stability from Atomic-Layer-Deposited Nickel Thin Film

Nickel silicide (NiSi) was formed by annealing a uniform low-resistivity nickel (Ni) film deposited by atomic layer deposition (ALD). A Ni film as-deposited at 220 °C exhibited the lowest sheet resistance of 18 Ω/sq. comparable to that of the film obtained by physical vapor deposition, even though it contained a significant amount of carbon from the metalorganic precursor. It is believed that the carbon is uniformly distributed in the film by partly forming a weak Ni3C phase which eliminates other crystalline defects in the film and hence lowers the resistance of the film. However, the carbon was not observed at the Ni/Si interface and in the silicon bulk except at the film surface after the annealing to form silicide. The existence of carbon at the surface of the film causes the film to maintain a low-resistivity NiSi phase up to 800 °C, without the carbon at the surface, the phase of film is changed to the high-resistivity nickel disilicide (NiSi2) at such a high temperature. The deposition of Ni by ALD and the formation of low-resistivity NiSi with an increased temperature stability can be useful in fabricating advanced devices, such as nanometer scale complementally metal–oxide silicons (CMOSs) or three-dimensional (3-D) MOS devices like Fin-type field-effect transistors (Fin-FETs).

Effectiveness of Self-Carbon and Titanium Capping Layers in NiSi formation with Ni Film Deposited by Atomic Layer Deposition

We firstly deposit a Ni film, directly after removing the native oxide, by atomic layer deposition (ALD) using a N2-hydroxyhexafluoroisopropyl-N1 (Bis-Ni) precursor, H2 as the reactant gas and Ar purging gas at 220 °C at a deposition rate of 1.25 A/cycle. The as-deposited Ni and Ni3C films exhibited sheet resistances of 5 Ω/ (sample B) and 18 Ω/ (sample A), respectively. The formation of a Ni3C phase was easily controlled by varying the flow rate of the H2 reactant as above gas. A rapid thermal process (RTP) was then performed in a nitrogen ambient to form NiSi at different temperatures from 400 to 900 °C. We estimated the process window temperature for the formation of low-resistance NiSi to be between 600 and 800 °C for self-carbon and Ti capping layers, as below while in the case of only Ni deposition the process window temperature changes to 700 to 800 °C. The respective sheet resistances of the films were changed to 3 Ω/ (sample B) and 4 Ω/ (sample A) after silicidation. The reaction between Ni and Si could be increased by the self-carbon and Ti capping layers due to a decrease in the oxidation contamination and impurity incorporation in the Ni film during the silicidation process. This self-carbon capping layer is formed by the carbon-containing Ni3C phase, which segregates to the surface during the annealing process and forms a relatively thick surface layer. Additionally, this layer also protects the surface from oxygen contamination. The deposition of Ni by ALD and the improved formation of the low-resistance NiSi with increased temperature stability will be useful in the fabrication of advanced devices, such as nano meter-scale complementary metal oxide semiconductor (CMOS) or three-dimensional (3-D) devices.

Enhancement Mode Operation and Ultraviolet Responsivity of n-Channel GaN Metal?Insulator?Semiconductor Field Effect Transistor with Schottky Barrier Source and Drain

We investigated the electrical properties and photo-responsive characteristic of enhancement n-channel GaN Schottky barrier metal–insulator–semiconductor field effect transistor (SB-MISFET), which was fabricated on p-GaN grown on silicon substrate. Schottky type source and drain contacts were used to fabricate the enhancement type n-channel GaN MISFET without implantation. The electrical properties of fabricated device with 10 µm gate length and 100 µm width, exhibited a threshold voltage of 2.7 V, the maximum drain current of 1 µA/mm and the maximum transconductance of 0.4 µS/mm at VDS=10 V, and the drain leakage current density of less than 1 nA/mm2. The spectral photo-response characterization exhibits that the cutoff wavelength was 365 nm, and the UV/visible rejection ratio was about 110 near the threshold voltage at VDS=5 V.

Amphoteric Behavior of Impurities in GaN Film Grown on Si Substrate

Hall measurement presented that an unintentionally doped uniform and crack-free GaN film grown on n-type (111)-oriented Si substrate with high temperature-grown relatively thin AlN single and multiple buffer layer shows p-type conductivity. The position of valence band maximum at the surface of the film measured by the synchrotron radiation photoemission spectroscopy is below Fermi level at 1.09 eV due to band bending at the surface, which is indicative for the p-type nature of the grown film. The n-channel metal–oxide–semiconductor field effect transistor (MOSFET) fabricated on the GaN layer exhibited normally-off mode operation. This cannot be achieved if the GaN layer is not p-type. It is believed that the spatial coordination of auto-doped Si atoms, out-diffused from the substrate, or carbon complexes from metal-organic (MO) precursor favorably occupy the substitutional nitrogen site of the GaN film when the film is under tensile strain during the growth, which clearly explains that the p-type conduction is originated from the stress dependent amphoteric nature of Si atom and/or carbon complex in GaN.

Narrow Metal-Filled Trench as a Source/Drain Contact for Three-Dimensional Metal–Oxide–Semiconductor Field Effect Transistor

We proposed a novel narrow metal-filled trench as a source/drain contact structure for a three-dimensional (3D) metal–oxide–semiconductor field effect transistor (MOSFET) with self-aligned dual metal contacts or dual silicide contacts that can be fabricated by a simple process. We demonstrated experimentally that the proposed structure with a 30 nm narrow trench can be etched and filled. From the simulation, we found that the structure has lower sheet resistance and lower gate-to-source/drain parasitic capacitance than a conventional elevated source/drain contact structure, thereby fulfilling the ITRS requirements. This structure may be an alternative solution for source/drain contacts beyond 32 nm technology.

UV photo-responsive characteristics of an n-channel GaN Schottky-barrier MISFET for UV image sensors

The ultraviolet (UV) responsive properties of the enhancement-mode n-channel Schottky-barrier MISFET (SB-MISFET), which was fabricated on a p-type GaN layer grown on silicon substrate, were investigated. The drain leakage current of the MISFET is less than 1 nA/mm2, which is quite low compared to recently reported photodetectors. The MISFET exhibited a cutoff wavelength of 365 nm, and the UV/visible rejection ratio was about 120 near the threshold voltage. This is the first demonstration of the MISFET-type UV photodetector, which is highly applicable to the UV image sensors

Normally-Off GaN n-MOSFET with Schottky-Barrier Source and Drain on a p-GaN on Silicon Substrate.

We fabricated a schottky barrier metal oxide semiconductor field effect transistor (SB-MOSFET) for the first time on a p-GaN with silicon auto doping into the nitrogen site, grown on silicon substrate. The source/drain and gate metals were formed by aluminum and gold, respectively. PECVD SiO2was used as a gate dielectric. The fabricated devices exhibited threshold voltage of 1.65 V, and maximum transconductance of 1.6 mS/mm at VDS=5 V. The normalized on-current was 3 mA/mm and the off-current was as low as 3x10-9A/mm.

Properties and SPICE modeling for a Schottky diode fabricated on the cracked GaN epitaxial layers on (111) silicon

The planar Schottky diodes were fabricated and modeled to probe the device applicability of the cracked GaN epitaxial layer on a (111) silicon substrate. On the unintentionally n-doped GaN grown on silicon, we deposited Ti/Al/Ni/Au as the ohmic metal and Pt as the Schottky metal. The ohmic contact achieved a minimum contact resistivity of after annealing in an ambient at for 30 sec. The fabricated Schottky diode exhibited the barrier height of 0.7 eV and the ideality factor was 2.4, which are significantly lower than those parameters of crack free one. But in photoresponse measurement, the diode showed the peak responsivity of 0.097 A/W at 300 nm, the cutoff at 360 nm, and UV/visible rejection ratio of about . The SPICE(Simulation Program with Integrated Circuit Emphasis) simulation with a proposed model, which was composed with one Pt/GaN diode and three parasitic diodes, showed good agreement with the experiment.

Superior contact properties of trench filled contact for 3D MOSFET

In this paper, we examined the applicability of the trench filled contact technique for the self-aligned dual metal contact for 3D MOSFET through both experiments and simulation. The proposed contact technique has the lower parasitic resistance and capacitance compared with the conventional silicide and with the elevated source/drain structure. Using this technique, the ITRS requirement for the source/drain contact resistance can be satisfied.