Heon-Mo Koo

Test generation using SAT-based bounded model checking for validation of pipelined processors

Functional verification is one of the major bottlenecks in microprocessor design. Simulation-based techniques are the most widely used form of processor verification. Efficient test generation is crucial for the simulation-based verification. We present an efficient test generation methodology using SAT-based bounded model checking (BMC). This paper addresses two important challenges in test generation using SAT-based BMC: determination of bound for each property, and application of design and property decompositions to improve test generation time as well as memory requirement. Our experimental results using a MIPS processor demonstrate the feasibility and usefulness of our approach.

Functional Test Generation using Property Decompositions for Validation of Pipelined Processors

Functional validation is a major bottleneck in pipelined processor design. Simulation using functional test vectors is the most widely used form of processor validation. While existing model checking based approaches have proposed several promising ideas for efficient test generation, many challenges remain in applying them to realistic pipelined processors. The time and resources required for test generation using existing model checking based techniques can be extremely large. This paper presents an efficient test generation technique using decompositional model checking. The contribution of the paper is the development of both property and design decomposition procedures for efficient test generation of pipelined processors. Our experimental results using a multi-issue MIPS processor demonstrate several orders-of-magnitude reduction in memory requirement and test generation time

Functional test generation using design and property decomposition techniques

Functional verification of microprocessors is one of the most complex and expensive tasks in the current system-on-chip design methodology. Simulation using functional test vectors is the most widely used form of processor validation. A significant bottleneck in the validation of such systems is the lack of automated techniques for directed test generation. While existing model checking--based approaches have proposed several promising ideas for automated test generation, many challenges remain in applying them to industrial microprocessors. The time and resources required for test generation using existing model checking--based techniques can be prohibitively large. This article presents an efficient test generation technique using decompositional model checking. The contribution of the article is the development of both property and design decomposition procedures for efficient test generation of pipelined processors. Our experimental results using a multi-issue MIPS processor and an industrial processor based on Power Architecture#8482; Technology demonstrate several orders-of-magnitude reduction in validation effort by drastically reducing both test generation time and test program length.

Directed Micro-architectural Test Generation for an Industrial Processor: A Case Study

Simulation-based validation of the current industrial processors typically use huge number of test programs generated at instruction set architecture (ISA) level. However, architectural test generation techniques have limitations in terms of exercising intricate micro-architectural artifacts. Therefore, it is necessary to use micro-architectural details during test generation. Furthermore, there is a lack of automated techniques for directed test generation targeting micro-architectural faults. To address these challenges, we present a directed test generation technique at micro-architectural level for functional validation of microprocessors. A processor model is described in a temporal specification language at micro-architecture level. The desired behaviors of micro-architecture mechanisms are expressed as temporal logic properties. We use decompositional model checking for systematic test generation. Our experiments using a processor based on the power architecture technology shows very promising results in terms of test generation time as well as test program length.

Specification-based compaction of directed tests for functional validation of pipelined processors

Functional validation is a major bottleneck in microprocessor design methodology. Simulation is the widely used method for functional validation using billions of random and biased-random test programs. Although directed tests require a smaller test set compared to random tests to achieve the same functional coverage goal, there is a lack of automated techniques for directed test generation. Furthermore, the number of directed tests can still be prohibitively large. This paper presents a methodology for specification-based coverage analysis and test generation. The primary contribution of this paper is a compaction technique that can drastically reduce the required number of directed test programs to achieve a coverage goal. Our experimental results using a MIPS processor and an industrial processor (e500) demonstrate more than 90% reduction in number of directed tests without sacrificing the functional coverage goal.

Language-driven Validation of Pipelined Processors using Satisfiability Solvers

Due to increasing demand for faster computations, deeply pipelined processor architectures are being employed to meet desired system performance. Functional validation of such pipelined processors is one of the most complex and expensive tasks in the current systems-on-chip design methodology. While language-based validation techniques have proposed several promising ideas, many challenges remain in applying them to realistic pipelined processors. This paper describes two practical challenges in this methodology: test generation and equivalence checking. The time and resources required for test generation using the existing approaches can be extremely large for todays pipelined processors. Similarly, traditional equivalence checkers are not useful in the context of language-driven model generation and functional validation. This paper outlines our plan to address these challenges using satisfiability checking

Modeling and Specification of SoC Designs

System-level specifications are widely used to capture a wide spectrum of SoC designs. To enable early stage exploration, it is required that system-level specifications should have both formal (unambiguous) semantics and easy correlation with the architecture manual. However, most system-level specifications are still written in an informal manner. Since informal specifications are not amenable to automated analysis, there are possibilities of ambiguity, incompleteness, and contradiction, which can lead to different interpretations of specifications. This chapter introduces two of the most widely used system-level specifications: SystemC TLMs for hardware modeling, and UML activity diagrams for software modeling. To enable the automated validation, this chapter presents how to extract formal models from these specifications.

Learning-Oriented Property Decomposition Approaches

When checking a large design with complex properties (i.e., properties with large cone of influence or deep bounds), BMC-based methods are very costly since large SAT instances indicate long SAT search time. Although design and property decomposition techniques described in Chap. 8 are promising in reducing test generation complexity, laborious human intervention is inevitable during the composition of subtests. To improve the test generation performance using SAT-based BMC, this chapter presents an efficient approach that can spatially and temporally decompose the functional scenarios described by the specified properties. By using decision ordering-based learning, the process of subtest composition can be fully automated.

Functional Test Compaction

Validation of System-on-Chip designs involves huge amounts of functional test data. A lot of test compaction techniques have been proposed in manufacturing test domain because they have a significant impact on overall testing cost and time. However, there is limited progress in functional test compaction in validation domain because functional tests are considered as one-time effort in design methodology. Nevertheless, millions of tests are used in the current industrial practice, and regression testing is conducted regularly during design cycle. Therefore, reduction in functional tests will have significant impact on overall design effort by removing redundant tests as well as selecting effective tests. This chapter presents an efficient test compaction technique to reduce the functional test set.

Reuse of System-Level Validation Efforts

Transaction-level modeling (TLM) is widely used to enable early exploration for both hardware and software designs. It can reduce the overall design and validation effort of complex system-on-chip (SoC) architectures. However, due to lack of automated techniques coupled with limited reuse of validation efforts between different abstraction levels, SoC validation is becoming a major bottleneck. This chapter presents a novel top-down methodology for automatically generating register transfer level (RTL) tests from TLM tests. Case studies using a router example and a 64-bit Alpha AXP pipelined processor demonstrate that the presented approach can achieve intended functional coverage of the RTL designs as well as can capture various functional errors and inconsistencies between specifications and implementations.