Heonchul Park

Area efficient VLSI architectures for Huffman coding

In this paper, we present simple and area efficient VLSI architectures for Huffman coding, an industrial standard proposed by MPEG, JPEG, and others. We use a memory of size O(n log n) bits to store a Huffman code tree, where a is the number of symbols. This storage scheme supports real-time encoding and decoding. In addition, few simple arithmetic operations are performed on the chip for encoding and decoding. Based on our scheme, we show a design for I-bit symbols. The proposed design requires 256*9 and 64*18-bit memory modules to process 8-bit symbols. The chip occupies a silicon area of 3.5*3.5 mm/sup 2/ using 1.2 micron CMOSN standard library cells. Compared with a known parallel implementation which requires up to 65536 PEs, the proposed architecture leads to a single PE design. It requires significantly less area than the known single PE design. Different Huffman codes can be stored by changing the contents of the memory, without changing the design. >

A fast algorithm for computing a histogram on reconfigurable mesh

The reconfigurable mesh captures salient features from a variety of sources, including the content addressable array parallel processor, the CHiP, the polymorphic-torus network and the bus automaton. It consists of an array of processors interconnected by a reconfigurable bus system. The bus system can be used to dynamically obtain various interconnection patterns between the processors. In this paper, we present a fast algorithm for computing the histogram of an N/spl times/N image with h grey levels in O(min{/spl radic/h+log*(N/h),N}) time on an N/spl times/N reconfigurable mesh assuming each PE has a constant amount of local memory. This algorithm runs on the PARBUS and MRN/LRN models. In addition, histogram modification can be performed in O(/spl radic/h) time on the same model. A variant of out algorithm runs in O(min{/spl radic/h+log log(N/h),N}) time on an N/spl times/N RMESH in which each PE has constant storage. This result improves the known time and memory bounds for histogramming on the RMESH model. >

Modular VLSI architectures for real-time full-search-based vector quantization

Vector quantization (VQ) has become feasible to be employed for real-time applications by using VLSI technology. In this paper, the authors propose modular linearly connected VLSI architectures for VQ that can support real-time image processing applications. Each processing element in the design consists of an adder and a shift register instead of a multiplier. The designs require fixed I/O bandwidth with the host and allow codebook changes. The throughput is independent of the codebook size. These designs can be extended to the case when a fixed number of processors are available. A number of VQ schemes-single-stage and multistage VQ, classified VQ, etc.-can be implemented using this approach. >

A 26mW dual-mode RF receiver for GPS/Galileo with L1/L1F and L5/E5a bands

A CMOS RF receiver for L1/L1F and L5/E5a dual-band GPS/Galileo system is designed in a 0.13 m standard CMOS process. It can be fully integrated in System-on-Chip (SoC) solution for GPS and Galileo. The receiver includes a low-noise amplifier (LNA), down-conversion mixers, channel selection filters (CSF), 2-bit analog-to-digital converters (ADC) and the full phase-locked-loop (PLL) synthesizers as well as on-chip voltage-controlled-oscillator (VCO). The dual-band LNA achieves a noise figure (NF) of 2.2 dB and a gain of 16 dB for each band. The PLL exhibits phase noise of -90 dBc/Hz at 100 kHz offset frequency. The receiver consumes 26 mW for a supply voltage of 1.2 V while occupying a 3times3.8 mm2 die area including ESD I/Q pads.

An optimal multiplication algorithm on reconfigurable mesh

An O(1) time algorithm to multiply two K-bit binary numbers using an N/spl times/N bit-model of reconfigurable mesh is shown. It uses optimal mesh size and it improves previously known results for multiplication on the reconfigurable mesh. The result is obtained by using novel techniques for data representation and data movement and using multidimensional Rader Transform. The algorithm is extended to result in AT/sup 2/ optimality over 1/spl les/t/spl les//spl radic/N in a variant of the bit-model of VLSI.

Area efficient fast Huffman decoder for multimedia applications

Proposes an area-efficient VLSI architecture for fast Huffman decoder which can support HDTV rates. Huffman coding, which is known as optimal variable length coding, has been widely used to reduce storage and communication channel bandwidth, and several emerging image compression standards such as JPEG, MPEG, CCITT H.261 require to perform Huffman coding in real-time with high throughput. However, most known designs are not suitable for real-time operation or for implementation, especially in HDTV, since these require large amount of VLSI area or a large number of processing elements (PEs) for high performance. The proposed VLSI architecture for the Huffman decoder requires fewer comparators and smaller size of data rotator to simulate the Barrel shifter. It can decode up to 17 bits per cycle and employs a 40 MHz clock which can support HDTV rates. Thus, it can decode Huffman coded sequences up to 680 Mbits/s at peak. Compared with the parallel implementation in Mukherjee et al. (1991) which requires upto 1460 PEs and has 10 Mbps of throughput, the proposed architecture is a single PE design with competitive processing power. It requires 25% of the area of the known single PE design in Lei and Sun (1991).

A L1-Band RF receiver for GPS aplication in 0.13um CMOS technology

This paper presents a L1-Band RF receiver for GPS application in 0.13 mum CMOS technology. The receiver is based on a 4.092 MHz low-IF architecture to alleviate the DC-offset problem. It includes a low-noise amplifier (LNA), a down-conversion mixer, a bandpass filter, and variable gain amplifier (VGA). The gain of VGA is controlled digitally by the digital gain controller and the total dynamic range of the baseband part is 60 dB. The franctional-N frequency synthesizer with sigma-delta modulator is used to allow multiple reference clock frequencies. The phase noise is -123 dB/Hz at 1 MHz offset. The whole receiver dissipates 45 mW with 1.2 V supply. And the system noise figure (NF) is 4 dB.

A fast algorithm for performing vector quantization and its VLSI implementation

In this paper, we propose a new tree search algorithm for performing vector quantization (VQ), and a processor and area efficient architecture for implementing it. The proposed algorithm consists of two phases: in the first phase, we perform a fast approximate search without using multiplication. In the second phase, we employ a known tree search algorithm on the neighborhood of the codevector found in the first phase. The size of the search space in the second phase depends on the desired image quality. For obtaining image quality comparable to the known tree (full) search based VQ, the proposed algorithm takes O(klogloglogN) (O(kloglogN)) time units, where N is the number of codevectors and k is the number of dimensions. In the proposed architecture, O(logloglogN) and O(loglogN) processing elements are used to obtain image quality which is comparable to those produced by the known tree search and full search based VQ, respectively. These implementations support real time operations.<<ETX>>