Hera Antonopoulou

Machine-printed from handwritten text discrimination

This paper deals with the discrimination between machine-printed and handwritten text, a prerequisite for many OCR applications. An easy-to-follow approach is proposed based on an integrated system able to localize text areas and split them in text-lines. A set of simple structural characteristics that capture the differences between machine-printed and handwritten text-lines is presented and preliminary experiments on document images taken from databases of different languages and characteristics show a remarkable performance.

Cleaning and enhancing historical document images

In this paper we present a recursive algorithm for the cleaning and the enhancing of historical documents. Most of the algorithms, used to clean and enhance documents or transform them to binary images, implement combinations of complicated image processing techniques which increase the computational cost and complexity. Our algorithm simplifies the procedure by taking into account special characteristics of the document images. Moreover, the fact that the algorithm consists of iterated steps, makes it more flexible concerning the needs of the user. At the experimental results, comparison with other methods is provided.

Distributed Protocols Against Mobile Eavesdroppers

We propose and study the following pursuit-evation problem in distributed enviroments: Members of a team of guards (e.g. antivirus programs) traverse the links of a network represented by a graph G, in pursuit of a fugitive (e.g. worm) which moves along the links of the graph without any other knowledge about the locations of the guards than whatever it can collect as it moves (e.g. the worm is oblivious to dynamic network behaviour). The fugitives purpose is just to read local information at each node and to stay in the net as long as possible. When a guard meets a fugitive, the fugitive is destroyed. We combinatorially characterize and compare such problems, and we present network protocols that allow an efficient (in terms of number of guards and messages) elimination of the fugitive. Note that the problem we study is fundamentally different from distributed graph searching, since the fugitive does not know the locations of the guards. Our protocols make use of accidental meetings in random walks. The analysis and the proof techniques are based on a novel extension of multiple, parameterized random walk properties which may be of independent theoretical interest.

Test Set Embedding into Low-Power BIST Sequences Using Maximum Bipartite Matching

Current trends in VLSI designs necessitate low power during both normal system operation and testing activity. Traditional Built-in Self Test (BIST) generators rise unnaturally the power consumption during testing, boosting the need to add low-power solutions to the arsenal of BIST pattern generators. In this paper, the utilization of gray code generators is proposed as a low-power BIST solution. More precisely, we show how the time required to apply a given test pattern can be decreased, by switching between different gray sequences during the application of the test set. Experimental results indicate that the time required to embed the test set within a low-power sequence is reduced to almost 50%, compared to a previously proposed solution.

Output response compaction in RAS-based schemes

Scan design has been the backbone of design for testability schemes in industry because it provides for controllability and observability of the internal flip flops of the circuit. However, the serial scan causes high switching activity during testing which results in high power dissipation. Another problem that may appear in scan designs is unknown values, which can invalidate the final signature captured in the response verifier.

On Embedding Test Sets into Hardware Generated Sequences

In this paper a novel algorithm is presented for embedding test sets containing don’t care values into sequences generated by binary counters. Experiments carried out on randomly generated test sets reveal that the proposed scheme results in shorter test sequences compared to randomly filling the don’t care bits with ‘0’ and ‘1’ values. Furthermore, comparison with schemes that have been proposed in the open literature for embedding test sets into hardware-generated sequences reveal that the proposed schemes presents comparable results, while in many cases it performs better.

A Novel SRAM-Cell Based Input Vector Monitoring Concurrent BIST Architecture

Input vector monitoring concurrent Built-In Self-Test (BIST) schemes can circumvent problems appearing separately in on-line and off-line BIST techniques. The concurrent test latency of an input vector monitoring concurrent BIST scheme is the time required in order to complete the concurrent test. In this paper a novel input vector monitoring concurrent BIST scheme is presented. The proposed BIST scheme is shown to have lower hardware overhead for the same values of the concurrent test latency compared to previously proposed schemes.

On threshold properties

Abstract In this paper we consider two random graph models and their relationship. More specifically, we consider the random graph model Gn,m , where a random graph is constructed by drawing uniformly and independently m edges out of the possible edges without repetition, and the random graph model Gn,mm where a random graph is constructed by the same process, but the an edge is allowed to be selected more than once. We prove that the property of a random graph G of the latter model having multiple edges is a threshold property, with threshold function t(n) = n. Moreover, if m = cn for some positive real number c, then the probability that a random graph G has multiple edges approaches exp(–c 2).