Herbert Taucher

A netlist-level fault-injection tool for FPGAs

A fault-injection tool can be very interesting in context to safety-critical applications, e.g., to test fault-detection and avoidance mechanisms or simply to stress an application and analyze its behavior when faults occur. In this work, a fault-injection tool is presented which can be used to instrument an FPGA design with fault-injection logic on netlist level during the implementation phase and to inject faults during runtime afterwards. The proposed approach can be smoothly integrated into an industrial FPGA tool flow, supports devices from multiple FPGA vendors and is highly configurable in order to fit to the number of available FPGA logic resources. Differences to related approaches which are applied on either HDL- and netlist-level as well as on the FPGA configuration bitstream are described. Finally, some results are presented to prove the applicability of the proposed solution.ZusammenfassungTools zur Fehlerinjektion können speziell im Kontext von sicherheitskritischen Applikationen hilfreich sein, um etwa Mechanismen zur Fehlererkennung und -vermeidung zu testen oder das Verhalten einer Applikation im Fehlerfall zu überprüfen. Diese Arbeit beschreibt ein derartiges Werkzeug, das es erlaubt, ein FPGA-Design mit Zusatzlogik zur Fehlerinjektion im Zuge der Implementierungsphase auf Netzlisten-Ebene zu instrumentieren und danach zur Laufzeit Fehler am FPGA einzustreuen. Das vorgestellte Tool fügt sich in einen industriellen FPGA Tool Flow ein, unterstützt Devices verschiedener FPGA-Hersteller und kann durch entsprechende Konfiguration an die verfügbaren FPGA-Ressourcen angepasst werden. Die Arbeit geht auf Unterschiede zu existierenden Lösungen ein, die auf HDL- oder Netzlisten-Ebene, aber auch direkt im FPGA-Konfigurations-Bitstream Fehler injizieren. Schlussendlich werden einige Implementierungsergebnisse präsentiert, welche die Sinnhaftigkeit des vorgestellten Ansatzes belegen.

Logic synthesis of assertions for saftey-critical applications

In this work we propose the rather new approach to synthesize properties formulated in verification languages, in particular PSL, down to hardware level. Such flow can be useful especially for safety-critical applications to automatically generate runtime monitors at little additional design efforts. Existing assertion synthesis tools from both academia and industry are presented as well as evaluation results concerning their features and drawbacks. The main part of this work focuses on the development of a proposed own tool flow which could benefit from available commercial and/or open-source tools like PSL parsers and equivalence checkers. The paper concludes with an outlook to future work in order to smoothly integrate our proposed approach into an existing state-of-the-art FPGA design flow. First resource estimations from previous work showed that optimized hardware assertion checkers may make up only a few percentage of the designs complete size.