Hervé Chanal

The LHCb trigger and its performance in 2011

The LHCb trigger and its performance based on data taken at the LHC in 2011 is presented. LHCb is designed to perform flavour physics measurements, and its trigger distinguishes charm and beauty decays from the light quark background. It uses a combination of lepton identification of particles, transverse momentum of particles and selects particles originating from hadrons which decay after a finite flight distance. The trigger reduces the

PACIFIC: A 64-channel ASIC for scintillating fiber tracking in LHCb upgrade

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Time alignment of the front end electronics of the LHCb calorimeters

MHz of bunch-bunch crossings with at least one non-elastic pp-interaction to 3 kHz of events which are written to storage in two trigger levels. The first level is implemented in hardware, while the next level is a software application which runs on all processors of a large computer farm. A data driven method is used to evaluate the performance of the trigger for several charm and beauty decay modes.

PACIFIC: Silicon photomultiplier readout ASIC for the LHCb upgrade

The LHCb detector will be upgraded during the next LHC shutdown in 2018/19 [1]. The tracker system will have a major overhaul. Its components will be replaced with new technologies in order to cope with the increased hit occupancy and radiation environment. Here we describe a detector made of scintillating fibers read out by silicon photomultipliers (SiPM), with a view to its application for this upgrade. This technology has been shown to achieve high efficiency and spatial resolution, but its integration within a LHCb experiment presents new challenges. This article gives an overview of the R&D status of the low-Power ASIC for the sCIntillating FIbres traCker (PACIFIC) chip implemented in a 130 nm CMOS technology. The PACIFIC chip is a 64-channel ASIC which can be connected to a SiPM without the need of any external component. It includes analog signal processing and digitization. The first stage is a current conveyor followed by a tunable fast shaper (≈10 ns) and a gated integrator. The digitization is performed using a 3 threshold non-linear flash ADC operating at 40 MHz. The PACIFIC chip has the ability to cope with different SiPM suppliers with a power consumption below 8 mW per channel and it is radiation-tolerant. Lastly, simulation and test results show the proper read out of the SiPMs with the PACIFIC chip.

PACIFIC: the readout ASIC for the SciFi Tracker of the upgraded LHCb detector

LHCb is the experiment at the Large Hadron Collider at CERN designed for performing studies of CP-symmetry violation and rare decays of B-hadrons. Its calorimeter system allows to trigger on photons and electrons by associating the information from a scintillating pad signing charged particle (SPD), a pre-shower tagging electromagnetic particles (PS), an electromagnetic calorimeter (ECAL) and a hadronic calorimeter (HCAL). We present the principles and procedures for the fine time-alignment throughout the commissioning and the first collision phases. We give a particular emphasis to the choices made in the electronic design of the calorimeters to deal with the signal shape and spill over. Also we summarise the achieved levels of synchronisation.

A front-end chip development for the sLHC CMS Silicon Strip Tracker

PACIFIC is a 64 channel mixed-signal ASIC designed for the readout of the Scintillating Fibre (SciFi) Tracker developed for the LHCb upgrade in 2018/19. The SciFi Tracker uses as active material 250 μm scintillating fibres, stacked in 6 layer mats and sensed by custom designed 128 channel silicon photomultiplier (SiPM) arrays. It will be comprised of 12 planes, each covering an area of 5×6 m2. PACIFIC is connected directly to the SiPM arrays without any interface components, using a current conveyor to acquire the current pulses coming from these sensors. The following stage is a fast shaper with a fully configurable double pole-zero cancellation scheme, which reduces the pulse width and thus the spillover. Subsequently, the signal is accumulated with a gated integrator, using two interleaved units to maximize the integration time. Finally, the digitization is performed with a 2 bit non-linear flash ADC, bundling together the data from two channels and outputting them through a serializer at 160 Mbps. Altogether, the target power consumption is 10 mW per channel. Several prototypes have been produced using IBM and TSMC CMOS 130 nm process technology, including a full size prototype.

A front end chip development for the SLHC CMS Slicon Strip Tracker

The LHCb detector will be upgraded during the Long Shutdown 2 (LS2) of the LHC in order to cope with higher instantaneous luminosities and will switch to a 40 MHz readout rate using a trigger-less software based system. All front-end electronics will be replaced and several sub-detectors must be redesigned to cope with the higher detector occupancy and radiation damage. The current tracking detectors downstream of the LHCb dipole magnet will be replaced by the Scintillating Fibre (SciFi) Tracker. The SciFi Tracker will use scintillating fibres read out by Silicon Photomultipliers (SiPMs). State-of-the-art multi-channel SiPM arrays are being developed and a custom ASIC, called the low-Power ASIC for the sCIntillating FIbres traCker (PACIFIC), will be used to digitise the signals from the SiPMs. This article presents an overview of the R&D for the PACIFIC. It is a 64-channel ASIC implemented in 130 nm CMOS technology, aiming at a radiation tolerant design with a power consumption below 10 mW per channel. It interfaces directly with the SiPM anode through a current mode input, and provides a configurable non-linear 2-bit per channel digital output. The SiPM signal is acquired by a current conveyor and processed with a fast shaper and a gated integrator. The digitization is performed using a three threshold non-linear flash ADC operating at 40 MHz. Simulation and test results show the PACIFIC chip prototypes functioning well.

PACIFIC: SiPM readout ASIC for LHCb upgrade

The FEAFS chip has been designed for the upgrades of the CMS Silicon Strip Tracker, which is planned in view of the LHC high luminosity upgrade. Its primary function is to provide a 40 MHz selective readout of particle hits that will be used for the generation of the 100 kHz hardware trigger of the experiment within a latency of 6.4 μs. To achieve this goal, the chip identifies clusters of limited number of activated strips and correlated in position, in a given window, in two closely superimposed sensors connected to the same chip. Finally, trigger and DAQ data are transmitted off detector via a common link. The FEAFS chip has been developed in IBM 0.13 μm technology. This paper presents the design of the chip and test results.

Front-End Electronics for the LHCb Upgrade Scintillating Fibre Tracker

The FEAFS chip has been designed for a super-LHC CMS Silicon Strip Tracker front-end electronics. Its primary function is to find clusters of activated strips for the level 1 trigger. A filtering is done to remove clusters associated with low transverse momentum particles using either a cut on their width and/or a correlation between their positions on two modules [3]. The processing results are sent on a shared link with the readout data to lower the power consumption. The FEAFS chip has been developed in IBM 0.13µm technology. This paper presents the foreseen processing and the design of the chip. Some simulation results are reported.