Hideki Minari

Hole Transport Mechanism in Silicon and Germanium Nanowire Field Effect Transistors

Atomistic hole transport simulation based on nonequilibrium Greens function method and tight-binding approximation has been performed for silicon (Si) and germanium (Ge) p-type nanowire (NW) field-effect transistors (FETs) with the diameter ranging from 1.6 to 3 nm. Simulation results show that the drain current density increases with increasing NW diameter and the difference in the drain current between Si and Ge NW FETs becomes smaller with decreasing NW diameter.

Simulation of the effect of arsenic discrete distribution on device characteristics in silicon nanowire transistors

We have theoretically investigated the effects of random discrete dopant (RDD) distribution on the device characteristics in silicon nanowire (NW) transistors by performing non-equilibrium Greens function simulation combined with kinetic Monte Carlo method for generating RDD distribution. We show that a small number of dopant atoms diffusing into the channel have a significant impact on the threshold voltage (Vth) variation. We examine the dependence of the Vth variation on RDD distribution and find that the fluctuation can be significantly reduced by introducing side-wall gate spacers. We also find that the on-current fluctuation is mainly caused by randomness of As dopants in the source and drain extensions and hence is inherent in ultra-small NW transistors.

Nano-device simulation from an atomistic view

Fluctuations of device characteristics due to random discrete dopant (RDD) distribution are numerically investigated in ultra-small Si nanowire transistors. Kinetic Monte Carlo process simulation is performed to obtain realistic RDD distributions, whose effects on the transport characteristics are then analyzed by using a non-equilibrium Greens function (NEGF) method. Fluctuations due to atomic disorder near the Si/SiO2 interface are also investigated by performing molecular dynamics oxidation simulation for realistic atomic structure models and NEGF device simulation for transport characteristics.

Quasi-ballistic electron transport through silicon nanocrystals

Monte Carlo simulation of electron transport through a silicon nanocrystal array is performed to clarify the mechanism of high-energy electron emission from a porous silicon diode. The electronic states are calculated within an empirical tight-binding approximation. In the Monte Carlo simulation, optical-phonon emission and elastic tunneling processes are taken into account. It is found that initial electron acceleration, which is enhanced due to the discrete nature of lower energy levels, plays an essential role in generating high-energy electron emission.

Effects of Strained Layers on Zener Tunneling in Silicon Nanostructures

An atomistic transport simulation based on the nonequilibrium Greens function and empirical tight-binding methods has been performed for one-dimensional Si n–i–n devices having a thin strained layer in the central i-region. Simulation results show that introducing a strain layer strongly enhances the Zener tunneling current for both tensile and compressive strain.

Strain effects on hole current in silicon nanowire FETs

Hole transport simulation based on the nonequilibrium Greens function and tight-binding formalism has been performed for strained Si nanowire FETs with a diameter of 1.5nm and 2.5 nm. Simulation results show that for Si nanowire FETs with a diameter of 2.5 nm, the compressive strain enhances the ballistic hole current, while the tensile strain gives opposite results. For Si nanowire FETs with a diameter of 1.5 nm, the ballistic hole current hardly depends on the strain magnitude.

Ellipsoidal Band Structure Effects on Maximum Ballistic Current in Silicon Nanowires

Silicon Nanowires Nobuya Mori1,3, Hideki Minari1,3, Shigeyasu Uno2,3, and Junichi Hattori2,3 1Division of Electrical, Electronic and Information Engineering, Graduate School of Engineering Osaka University, Suita, Osaka 565-0871, Japan Phone: +81-6-6879-7731, E-mail: nobuya.mori@eei.eng.osaka-u.ac.jp 2Department of Electrical Engineering and Computer Science, Graduate School of Engineering Nagoya University, Nagoya, Aichi 464-8603, Japan 3CREST, JST, 5 Sanbancho, Chiyoda-ku, Tokyo 102-0075, Japan

Impact of Interface Roughness on Threshold-Voltage Variation in Ultrasmall Gate-All-Around and Double-Gate Field-Effect Transistors

Effects of interface roughness on the threshold-voltage variation of nanometer-size gate-all-around (GAA) and double-gate (DG) metal–oxide–semiconductor field-effect transistors (MOSFETs) are investigated using three-dimensional non-equilibrium Greens function formalism. It is found that DG MOSFETs have better robustness to the interface roughness compared to GAA MOSFETs. This is attributed to the fact that the GAA structure has additional quantum conferment along the gate-width direction of the DG structure. From numerical simulations, a simple analytical formula is derived, which describes the threshold-voltage variation in terms of the subband energy change and reduction in the transmission function.

Strain effects on ballistic current in ultrathin DG SOI MOSFETs

Atomistic electron transport simulation based on a nonequilibrium Greenpsilas function method and a tight-binding approximation has been performed for h110i-channel strained Si ultrathin double-gate silicon-on-insulator MOSFETs on a (100) substrate. Simulation results show that the tensile strain enhances the ballistic current, while the compressive strain gives opposite results.

Impact of Strain on Ballistic Current in Si n–i–n Structures

Atomistic transport simulation based on the nonequilibrium Greens function and empirical tight-binding methods has been performed for one-dimensional strained Si n–i–n devices. Simulation results show that the tensile strain enhances the ballistic current and reduces the Zener tunneling current, while the compressive strain gives opposite results.