Hideki Ohashi
Sanyo
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Featured researches published by Hideki Ohashi.
IEEE Transactions on Consumer Electronics | 1988
Osamu Ikeda; Toshiyuki Hakoda; Mituyoshi Fukuda; Hideki Ohashi; Masahisa Shimizu
The authors describe the D/sup 2/SP digital signal processor which is designed with a dual processor architecture, and is especially effective for stereo audio signal processing. The D/sup 2/SP has two independent processor units, the left processor and right processor. The D/sup 2/SP contains an audio data interface, external dynamic random-access memory (DRAM) interface, microcomputer interface, and a sequence controller. The single chip D/sup 2/SP is capable of performing audio signal processing needed for graphic equalizers, surround, and sound power spectrum calculation. The dual processor mainly consists of a 24-bit multiplier with a 108-ns cycle time and is assembled on a single chip fabricated from 1.2- mu m CMOS technology. The total number of integrated transistors is approximately 300 K. Applications, such as use as a seven-band graphic equalizer, seven-band power spectrum calculator, and surround sound processing, are briefly discussed. >
Archive | 2006
Akira Iketani; Hideki Ohashi
Archive | 1993
Mituyoshi Fukuda; Masahisa Shimizu; Hideki Ohashi; Masaki Kawaguchi
Archive | 2007
Takeo Inoue; Hideki Ohashi; Yoshitaka Onaya
Archive | 2006
Takashi Kuroda; Iwao Honda; Noriyuki Tomita; Hideki Ohashi
Archive | 1988
Mituyoshi Fukuda; Masahisa Shimizu; Hideki Ohashi; Masaki Kawaguchi
Archive | 2008
Takeo Inoue; Hideki Ohashi
Archive | 2007
Takeo Inoue; Hideki Ohashi
Archive | 2006
Hideki Ohashi; Kozo Okuda; Takeo Inoue
Archive | 2006
Iwao Honda; Hideki Ohashi; Takashi Kuroda; Noriyuki Tomita