Hideki Sawaguchi

Investigation of 2 Gb/in/sup 2/ magnetic recording at a track density of 17 kTPI

Developments of magnetic head, recording medium, positioning, and signal processing technologies made it possible to perform magnetic recording at an areal density of 2 Gb/in/sup 2/ on a prototype 3.5-in diameter hard disk drive. A track density of 17 kTPI, which is comparable to or even greater than that used in optical storage systems, is used to minimize the reduction in the physical clearance between the medium and the head. The authors outline the system and its component technologies. The read/write characteristics of the 3.5-in prototype disk system are also reported. >

Concatenated error correction coding for high-order PRML channels

A modified E/sup 2/PRML (ME/sup 2/PRML) channel is optimized for high-density magnetic recording in order to reduce long error-propagation events in an ML detector. A cyclic redundancy-check error-correction code (CRCC), an innerblock ECC concatenated to the ML detector, is introduced as a new ECC-coding scheme for the high-order partial response maximum likelihood (PRML) channel. The CRCC coding can efficiently improve the BER performance with only a few redundant check-bits which intensively correct most-dominant short error-events in the ME/sup 2/PRML detector. A 16/17 coded ME/sup 2/PRML channel in conjunction with a 2.9% redundant CRCC coding can achieve a gain of more than 35 dB over a conventional 16/17 coded EPRML channel at a user density of 2.8.

A 150 Mb/s PRML chip for magnetic disk drives

Recent magnetic disk drives require high transfer rates and recording densities. PRML signaling is now prevalent in digital read/write channels. This PRML chip operates at a maximum data rate of 150 Mb/s with 1550 mW and includes all basic functions such as servo demodulation and write pre-compensation for magnetic disk drives with optimized circuit size. The chip is fabricated in 0.7 /spl mu/m double-poly double-metal BICMOS suitable for low-power devices and is packed in a 100-pin quad flat package with a die approximately 7 mm/sup 2/. This chip has a single 5 V power supply.

Noise characteristics of double-layered perpendicular media

Abstract Time-domain analysis of a reproduced waveform shows that the media noise of double–layered perpendicular media consists of transition noise localized around the transitions and DC-erased area noise independent of transition. We used this analysis to develop a waveform model, incorporating media noise, to estimate the bit error rate performance of double-layered perpendicular media. Moreover, we proposed a simple mathematical method for estimating the media noise power using the head/media magnetic parameters and R/W conditions.

Soft-output decoding for concatenated error correction in high-order PRML channels

A soft-output decoding scheme was developed for the cyclic-redundancy-check error-correction-code (CRCC) concatenated error correction by applying the list and soft-symbol-output Viterbi algorithm (list-SOVA). By focusing on just the specified dominant error-events in the maximum-likelihood (ML) sequence detector, a soft-output data-reliability generator and a list generator were efficiently simplified for soft-output decoding. The soft-output decoding enables multiple dominant error events within a data block to be corrected without increasing the CRCC redundancy and modifying the CRCC structure. It can also help prevent the CRCC miscorrection when correcting the multiple error-events. It was confirmed that the soft-output decoding with a reasonably sized data-block list can perfectly correct the double error-events within a data-block on a 16/17 rate quasi-MTR-coded modified E/sup 2/PRML (ME/sup 2/PRML) channel at a practical error-rate.

Torbo decoding for high-rate concatenated parity-check codes on PRML channels

A simple turbo decoding scheme is proposed for partial-response (PR) channels by using high-rate parity-check codes as an outer error-correction code (ECC). The use of the simple parity codes enables a simplified and high-speed implementation of the a posterior probability (APP) decoder. Its key feature is an iterative decoding step for the parallel concatenation of two parity-check outer codes connected via an interleaver. The parity iterative decoding can provide the high-rate parity-check outer codes with superior correction capability for random error-events, so it can help to reduce the decoding latency. The combination of the serial turbo decoding for a modified E/sup 2/PR (ME/sup 2/PR) channel and the parity iterative decoding demonstrated a coding gain of 4-5 dB at a bit error rate of 1.0E-5 for a coding rate of 8/9.

Soft-output post-processing detection for PRML channels in the presence of data-dependent media noise

A soft-output data-detection scheme optimized for data-dependent media-noise recording channels is proposed that uses signal-dependent correlation-sensitive (SDCS) metric estimation for post-processing decoding. This media-noise soft-output (MNS) decoding scheme achieves sub-optimal maximum-likelihood (ML) sequence detection in a non-stationary media-noise channel, while still using traditional Viterbi detection. Because it drastically reduces SDCS metric computation by focusing on only specified dominant error-events in the ML detector, it is less complex than other sub-optimal detection schemes. Moreover, its one-shot post-processing scheme enables the use of a simple lookup-table architecture suitable for high-speed circuit implementation. Simulation shows that the MNS decoding scheme in conjunction with a conventional ME/sup 2/PRML system provides an excellent tradeoff between data-detection performance and computation complexity for a media-noise-dominant high-density recording channel.

Performance analysis of soft-output post-processing detection for data-dependent media noise channels

A soft-output data-detection scheme optimized for data-dependent media-noise recording channels is investigated that uses signal-dependent correlation-sensitive (SDCS) metric computation for post-processing decoding. This media-noise soft-output (MNS) decoding scheme achieves suboptimal maximum-likelihood (ML) sequence detection in a nonstationary media-noise channel, while still using traditional Viterbi detection. Because it drastically reduces SDCS metric computation by focusing on correcting only the dominant error events in the ML detector, it is less complex than other suboptimal detection schemes. Moreover, the MNS decoding scheme provides parity-check-code decoding with more reliable soft-output information. Simulation showed that MNS decoding in conjunction with a conventional ME/sup 2/PRML system, provides an excellent tradeoff between data-detection performance and computation complexity for a jitter-noise dominant high-density recording channel.

Performance analysis of decision-feedback equalization with maximum-likelihood detector in high-density recording channels

The performance of decision-feedback equalization combined with maximum-likelihood detection (DFE/ML) using the FDTS/DF algorithm was estimated analytically in terms of the length of the feedback-filter and the depth of the ML-detector. Performance degradation due to error propagation in the feed-back loop and in the ML-detector was taken into account. It was quantitatively shown that signal-to-noise-ratio performance in high-density magnetic recording channels can be improved by combining an ML-detector and a feedback-filter. In particular, it was found that near-optimum performance can be achieved over the channel density range from 2 to 3 by increasing the total of the feedback-filter length and the ML-detector depth to six bits.

A PRML and EPRML spliced operation scheme designed to reduce power dissipation of read channel chips

In order to reduce the power dissipation and the circuit size for read channel chips, two techniques are proposed. One is based on the spliced operation of two different channel signaling methods such as PRML and EPRML. These two detectors are operated selectively in correspondence with the value of the reliability information extracted from the data series. The other is an extended method which applies the transformed trellis simplification technique to a RADIX4 detector. These are effective for implementing a high data transfer rate. We have confirmed that the total detector power dissipation including PRML, EPRML and additional circuits is reduced to less than half of the conventional EPRML power dissipation, while achieving twice the data transfer rate of the conventional EPRML.