Hidemi Noguchi

Fast optical channel recovery in field demonstration of 100-Gbit/s Ethernet over OTN using real-time DSP

A field trial of 100-Gbit/s Ethernet over an optical transport network (OTN) is conducted using a real-time digital coherent signal processor. Error free operation with the Q-margin of 3.2 dB is confirmed at a 100 Gbit/s Ethernet analyzer by concatenating a low-density parity-check code with a OTN framer forward error correction, after 80-ch WDM transmission through 6 spans x 70 km of dispersion shifted fiber without inline-dispersion compensation. Also, the recovery time of 12 msec is observed in an optical route switching experiment, which is achieved through fast chromatic dispersion estimation functionality.

A 40-Gb/s CDR Circuit With Adaptive Decision-Point Control Based on Eye-Opening Monitor Feedback

40-Gb/s clock and data recovery (CDR) circuit with an integrated high-precision eye-opening monitor (EOM) circuit and an adaptive control scheme for optimizing the data decision point are presented. An adaptive decision-point control (ADPC) scheme using the EOM feedback overcomes the time-varying waveform distortion due to transmission impairment, which causes severe degradation of bit-error-rate (BER) performance in high-speed (>40 Gb/s) data link systems. A 2.5 times 2.0-mm prototype chip is implemented in 0.18 -mum SiGe BiCMOS technology. The power consumption is 1.6 W with a +3.3-V supply voltage. Stable CDR operation with low-jitter performance (189 fs-rms) and the ADPC scheme using EOM feedback are demonstrated at 40 Gb/s. For a 30% duty-distorted 53 -mV signal, the proposed ADPC scheme drastically reduces the BER to le-12 compared to that (2e-7) without adaptive control. The experimental results demonstrate that the proposed CDR circuit greatly improves BER performance and provides robust CDR operation in high-speed data link systems.

A 40Gb/s multi-data-rate CMOS transceiver chipset with SFI-5 interface for optical transmission systems

As 40Gb/s optical communication systems enter the commercial stage, the transceiver, which is a key component of these systems, requires lower power dissipation, a size reduction, and a wider frequency range to meet the requirements of several standards, such as OC-768/STM-256 (39.8Gb/s), OTU-3 (43.0Gb/s), and 4×10GbE-LANPHY (44.6Gb/s). 40Gb/s transceivers have already been reported in SiGe-based technology.However, they dissipate more than 10W in total and do not support 39.8-to-44.6Gb/s wide-range operations [1–2]. There have been recent reports on CMOS transceivers, but their speed performance is still less than 40Gb/s and their output signal suffers from large jitter [3–5]. In this paper, 40Gb/s SFI-5-compliant TX and RX chips in 65nm CMOS technology consume 2.8W each. This low power dissipation allows for a small and low-cost plastic BGA package. The TX has a full-rate clock architecture that is based on a 40GHz VCO, a 40Gb/s retiming D-FF, and 40GHz clock-distribution circuits that lead to a low jitter of 0.57psrms and 3.1pspp at 40Gb/s. A 40/20GHz clock-timing-adjustment circuit based on a phase interpolator is used to ensure wide-range error-free operations (BER ≪ 10−12) at 39.8 to 44.6Gb/s. A quadruple loop architecture is introduced in the CDR circuit of the RX, resulting in a 38Gb/s error-free operation (BER ≪ 10−12) at 231−1 PRBS with a low rms jitter of 210fs in the recovered clock.

A 40 Gb/s Multi-Data-Rate CMOS Transmitter and Receiver Chipset With SFI-5 Interface for Optical Transmission Systems

A fully integrated 40 Gb/s transmitter and receiver chipset with SFI-5 interface is implemented in a 65 nm CMOS technology and mounted in a plastic BGA package. The transmitter chip provides good jitter performance with a 40 GHz full-rate clock architecture that alleviates pattern-dependent jitter and eliminates duty cycle dependence. The measured RMS jitter on the output is 570 fs to 900 fs over the range of 39.8 Gb/s to 44.6 Gb/s with a 231-1 PRBS pattern. The receiver chip operates over the range of 37 Gb/s to 41 Gb/s. The measured RMS jitter on the recovered clock is 359 fs to 450 fs. By taking advantage of CMOS technology, each chip achieves low power consumption of 2.8 W and full integration of SFI-5 functions, PRBS generators/error checkers, a DPSK precoder/decoder, and control interfaces in a 4.9 × 5.2 mm2 die.

A 9.9 G-10.8 Gb/s rate-adaptive clock and data-recovery with no external reference clock for WDM optical fiber transmission

A 9.9-10.8 Gb/s rate adaptive clock and data recovery circuit with 1:16 DMUX are integrated in 0.5 /spl mu/m SiGe BiCMOS. A dual-input voltage-controlled oscillator incorporates a fast and a slow tracking loop with a DC gain enhancer. The chip exhibits 2 mUIrms jitter generation and 0.45 UIpp jitter tolerance in a 4-80 MHz range. Power dissipation is 1.45 W from a 3.3 V supply.

A 40Gb/s CDR with Adaptive Decision-Point Control Using Eye-Opening-Monitor Feedback

In high-speed data link systems of over 40Gb/s, the data decision point in the CDR circuit is not often the optimum position of the eye diagram. The CDR circuit is fabricated using a 0.18 mum SiGe BiCMOS process. The ft and fmax are 200 GHz and 180 GHz, respectively. To overcome a severe degradation of BER performance due to this misalignment, a 40 Gb/s CDR circuit integrated with an adaptive decision-point control scheme by using an eye-opening monitor feedback is developed. The key approaches are 40 Gb/s high-precision eye-opening monitor (EOM) circuit to detect an optimum decision point, an adaptive decision-point control (ADPC) scheme by using the EOM feedback, a decision- point adjustable self-aligned phase detector to achieve the ADPC operation. The combination of these approaches improves both the BER performance and the stability of CDR operation.

A 35-to-46-Gb/s Ultra-Low Jitter Clock and Data Recovery Circuit for Optical Fiber Transmission Systems

We demonstrated an ultra-low jitter clock and data recovery (CDR) circuit that covers an ultra wide frequency range from 35 Gb/s to 46 Gb/s. Our CDR has a newly developed dual input LC-VCO with a fine/coarse tuning scheme and a dual-loop architecture, which consists of a phase tracking loop and a frequency tracking loop. The CDR chip, which was made using an InP-HBT process, shows an extremely clear eye opening with an ultra-low jitter (< 9 mUI-rms) and an error-free operation (<1times10-12) throughout a wide range of 35 to 46 Gb/s at a 231-1 PRBS signal. The RMS and peak-to-peak jitter of the recovered clock were 226 fs and 1.56 ps, respectively. We suppressed output jitter to half of that found in previous work. In addition, a stable bit error rate (BER) that is insensitive to PRBS word length was demonstrated during an optical transmission test. These results show that our full-rate CDR is a very promising chip for 40-Gb/s-class optical transmission systems with the multi data rates.

Experimental demonstration of the improvement of system sensitivity using multiple state trellis coded optical modulation with QPSK and 16QAM constellations

We evaluated experimentally 2, 8, 32 state 32Gbaud TCM-QPSK and TCM-16QAM. TCM offers finer configuration for flexible transponders increasing SE, on 1.1dB wider ranges. TCM may also be used with HD-FEC in lower power transceivers.

Long Haul transmission of four-dimensional 64SP-12QAM signal based on 16QAM constellation for longer distance at same spectral efficiency as PM-8QAM

We propose a new 4D coded modulation format, 64SP-12QAM, with same SE as PM-8QAM and straightforwardly-switchable with PM-16QAM. We experimentally demonstrated over 0.2 dB better sensitivity for 64SP-12QAM compared to PM-8QAM, enabling a transmission reach extension to 6,000 km at 6b/s/Hz.

Hardware-efficient multi-redundancy superposed trellis coded modulation on 16QAM constellation

We propose multi-redundancy optical coded modulation using superposed trellis. We experimentally prove that our scheme enables fine adaptive SE control and high coding gain of 7.1dB for 3-bit redundant 16QAM with quarterly reduced circuit complexity.