Hideo Sawamoto

2.5 V CMOS circuit techniques for a 200 MHz superscalar RISC processor

Novel 2.5 V CMOS circuit techniques including a noise tolerant precharge (NTP) circuit and a leakless buffer circuit are applied to a floating point macrocell for a 200 MHz superscalar RISC processor. The NTP circuit has two advantages: high noise immunity and high speed. Floating point operations can be executed in a two cycle latency using the high speed NTP circuit. The leakless buffer circuit with NMOS transmission gate in 128 floating point registers makes possible both high integration and low power dissipation, since the circuit causes no leak current without precharging the number of read lines. The processor makes use of 0.3 /spl mu/m CMOS technology with a 2.5 V power supply and four metal layers. The floating point macrocell has 380 thousand transistors and dissipates 350 mW at 200 MHz. The peak performance of the floating point macrocell is 400 MFLOPS.

A superscalar RISC processor with pseudo vector processing feature

A novel architectural extension, in which floating-point data are transferred directly from main memory to floating-point registers, has been successfully implemented in a superscalar RISC processor. This extension allows main memory access throughput of 1.2 Gbyte/s, and effective performance reaches 267 MFLOPS (89% of the peak performance) for typical floating-point applications. The processor utilizes 0.3-micron 4-level metal CMOS technology with 2.5 V power supply and contains 3.9 million transistors in 15.7 mm/spl times/15.7 mm die size. Only 4.5% of the die area is used for the extension. Pipeline stage optimization and scoreboard-based dependency check method allow the extension to be realized without affecting the operating frequency.

Programmable at-speed array and functional BIST for embedded DRAM LSI

A new approach to DFT (design for test) for an embedded DRAM LSI is proposed in This work. One powerful BIST engine is implemented on the LSI, which executes not only the array BIST for the DRAM and SRAM macros, but also functional BIST for the whole chip. It was implemented in an embedded DRAM cache LSI which is presented together with measured results.

A powerful yet ecological parallel processing system using execution-based adaptive power-down control and compact quadruple-precision assist FPUs

This paper reports the first trial in which spatially and temporally fine-grained power-down control has been implemented in a high-performance processor in the sense that the FPUs are controlled spatially and dynamically based on the execution sequence.

Design and Power Performance Evaluation of On-Chip Memory Processor with Arithmetic Accelerators

In this paper, we design an on-chip memory processor with arithmetic accelerators, which are expected to improve power consumption. In addition, we evaluate the power performance of the processor. We propose implementing vector-type arithmetic accelerators and SIMD-type arithmetic accelerators in the on-chip memory processor. The evaluation results obtained using our simulator indicate that the performance of the 4FMAs SIMD-type accelerators is similar to that of the 4FMAs vector-type accelerators on DAXPY, Livermore kernel 1 and 3. However, the performance of the 4FMAs vector-type accelerator exceeds that of the 4FMAs SIMD-type accelerator with respect to matrix multiplication and QCD because of difference in element size of the registers. On Livermore kernel 7, the power performance of the 4FMAs SIMD-type accelerators exceeds that of the 4FMAs vector-type because of register reuse. However, the 16FMAs vector-type accelerators have an advantage in almost all simulations, excluding main memory bandwidth intensive benchmarks.