Hideo Suzuki

Implementation and Experimental Evaluation of a Cryocooled System Prototype for High-Throughput SFQ Digital Applications

We report on development of a cryocooled system prototype for high-throughput single flux quantum (SFQ) digital applications. The system was designed to have 32 I/O links with a bandwidth of 10 Gbps/port. An SFQ multi-chip module (MCM), double mu-metal magnetic shields, a 40-K radiation shield, customized GaAs cryogenic amplifiers, a 32-pin wide-bandwidth cryo-probe, and 32 I/O cables were packaged in a vacuum chamber together with a two-stage 4-K 1-W Gifford-McMahon (G-M) cryocooler. S-parameter measurements showed that the analog bandwidth of the I/O link was 23 GHz. We demonstrated high-speed cryocooled operation of a test module, in which a 5 mm times 5 mm SFQ circuit chip was flip-chip bonded on a 16 mm times 16 mm MCM carrier with phi30 mum InSn bump bonds, at bit rates up to 12.5 Gbps. Measured bit error rate (BER) was less than 10-12 for a 1023 - 1 pseudorandom bit sequence (PRBS) at 10 Gbps.

AC Losses in YBCO Coated Conductors Subjected to Tensile Stress

Stress dependencies of AC transport current losses, magnetization losses and total losses were investigated applying tensile stresses to an YBCO (IBAD/PLD) conductor. Measured transport current losses showed slight stress dependence in the range of 0~1 GPa. That can be explained by stress dependence of the critical current of the conductor. The magnetization and total losses are less sensitive to the stress than the transport current losses

Superconductive Single-Flux-Quantum Circuit/System Technology and 40Gb/s Switch System Demonstration

This paper presents 40Gb/s I/O interface circuits and their application to an SFQ 2x2 switch system demonstration at 40Gb/s port speed, which is a four times improvement over previous work (Y. Kameda et al., 2007).

Dependence of AC Losses in HTS Coated Conductors With Magnetic Substrates on Tensile Stresses

We investigated uni-axial tensile stress dependence of AC losses (transport current, magnetization and total losses) in HTS coated conductor with magnetic Ni-alloy substrate. The AC loss characteristics are studied by relating to tensile stress dependence of critical currents of the conductor. Experimental results showed that the loss characteristics were different whether the critical current recovered the original value after the release of the stress or not. Dependence of AC loss characteristics on magnetic property of the substrate is also studied.

AC magnetization loss reduction by striation in YBCO-123/Hastelloy coated conductors

In the work we present experimental results of AC magnetization losses reduction due to striation process in YBCO-123/Hastelloy coated conductors. The measurements were carried out in a sinusoidally varying external magnetic field, with amplitudes up to 100 mT, in a frequency range of 8.5-85.4 Hz, and at temperature of 77 K. The field was oriented perpendicularly to the face of the tapes. Sample tapes were successively patterned into a form of narrow, parallel strips, by means of a photoresist lithography and chemical wet etching technique. Experimental results are discussed in a framework of existing theoretical models for energy dissipation in thin films in perpendicular AC magnetic fields.

Design and Implementation of an SFQ-Based Single-Chip FFT Processor

We have been working on the development of a high-speed fast Fourier transform (FFT) processor using single-flux-quantum (SFQ) logic circuits. In our previous studies, we designed and demonstrated a 4-bit butterfly processor, a data-shuffling circuit, and a twiddle factor ROM for 4-bit 8-point FFT using the AIST 10 kA/cm2 Nb advanced process 2 at maximum frequencies of 51.6, 59.5, and 51.5, respectively. In this study, to complete the FFT processor design, we designed and demonstrated residual component circuits called a rounding circuit and a data buffer at a target frequency of 50 GHz. We also designed and experimentally confirmed the operation of an SFQ-based single-chip FFT processor integrating all the component circuits.

Effect of Ion Implantation-Induced Defects on Leakage Current Characteristics of IEMOS

We investigated the relationship between ion implantation-induced defects and electrical characteristics, especially focusing on the leak failure rate in SiC IEMOSs and PN diodes. It was found that dislocation exists in each leakage point by analyzing identical leak-failed IEMOS by emission microscopy and refraction X-ray topography. The leak failure rate of the PN diodes and IEMOS was improved with an increase in the ion implantation temperature under the implantation and annealing conditions used in this experiment. It is considered that ion implantation-induced defects lead to an increase in leak failure rates, and also enable a decrease in leak failure rates by raising the implantation temperature up to 600 deg.C.

Experimental and simulation results of a symmetrical pad to reduce a stray ground current in superconducting integrated circuits

The method of extracting bias current is widely used in large scale SFQ circuits to avoid harmful effect by spreading the bias return current on a ground plane, which causes malfunction or degrading the operating margin by the stray magnetic field. Although extracting the bias current is effective, we found that the extraction using a normal pad structure with a bias pad and a current extracting pad still produces a large stray ground current (magnetic field) for its asymmetric structure. We proposed a bilaterally symmetrical pad structure, which can reduce the stray ground current significantly in superconducting circuits. The bias current is extracted from a nearby ground pad of a bias pad in usual method, whereas the bias current is extracted from two of the symmetrical ground pads which are arranged both sides of the bias pad in the symmetrical structure. Then, the bias current is extracted on halves from each of the two pads symmetrically, reducing the stray ground current. First, we have simulated the ground current by using FastHenry program. The results showed that the symmetrical pad structure outside of ground plane reduced spread of the ground return current significantly. Next, we have designed a test chip and confirmed the effectiveness of the symmetrical structure experimentally.

Measurement of low bit-error-rates of adiabatic quantum-flux-parametron logic using a superconductor voltage driver

Adiabatic quantum-flux-parametron (AQFP) is an energy-efficient superconductor logic. The advantage of AQFP is that the switching energy can be reduced by lowering operation frequencies or by increasing the quality factors of Josephson junctions, while keeping the energy barrier height much larger than thermal energy. In other words, both low energy dissipation and low bit error rates (BERs) can be achieved. In this paper, we report the first measurement results of the low BERs of AQFP logic. We used a superconductor voltage driver with a stack of dc superconducting-quantum-interference-devices to amplify the logic signals of AQFP gates into mV-range voltage signals for the BER measurement. Our measurement results showed 3.3u2009dB and 2.6u2009dB operation margins, in which BERs were less than 10−20, for 1 Gbps and 2 Gbps data rates, respectively. While the observed BERs were very low, the estimated switching energy for the 1-Gbps operation was only 2 zJ or 30kBT, where kB is the Boltzmanns constant and T is the...