Hideyuki Aoki

External memory BIST for system-in-package

This paper presents the design and implementation of an external memory built-in self-test (BIST) in system-on-chip (SoC) designed for system-in-package (SiP). We implemented the BIST handshaking with the internal bus in the microcontroller core for the purpose of enabling the BIST to access the CPU address space. This implementation allows to reduce the area overhead of the BIST and vary the test conditions flexibly according to each phase of debugging, reliability evaluation and mass-production test. For testing SDRAM and flash, we also designed a microcode based algorithmic pattern generator with enough loop-counters, an infinite looping function and a multiple command sequence generator. This BIST method was applied to consumer products with the IEEE 1149.1 JTAG TAP controller, and enabled multi-test for mass-production on a burn-in tester

SiP testing strategy for automobile LSI

Recently LSI for automobile is requested SiP or bare chip assembly. It is necessary for it to reduce the substrate size and to increase electrical performance. But current technology is satisfied with their request technically, but it is not reasonable in production cost. So I mention about Wafer level burn-in and Wafer level AC testing, which is necessary proceeding in the near future.