Hiroaki Ishiwata

Shared transistor architecture with diagonally connected pixels for CMOS image sensors

We have developed a pixel unit for CMOS image sensors (CISs) that has a shared transistor architecture with diagonally connected pixels. This pixel unit is composed of four photodiodes and seven transistors. It has a pixel size of 2.5-&mgr;m square. The transistors were designed using 0.18-micron aluminum process technology. Shared diffusion for reading signal electrons occurs between the corners of two photodiodes. The advantages of this layout include a long amplifier gate length and a large photodiode area.