Hiroaki Murakami

2.44-GFLOPS 300-MHz floating-point vector-processing unit for high-performance 3D graphics computing

A vector unit for high-performance three-dimensional graphics computing has been developed. We implement four floating-point multiply-accumulate units, which execute multiply-add operations with one throughput; one floating-point divide/square root unit, which executes division and square-root operations with six cycles at 300 MHz; and one vector general-purpose register file, which has 128 bits/spl times/32 words. The parallel execution of all units delivers a peak performance of 2.44 GFLOPS at 300 MHz.

Vector unit architecture for emotion synthesis

Two vector units embedded in the emotion engine chip support high-quality 3D graphics, emotion synthesis, and 300-MHz, 5.5-GFLOPS operation for the recently introduced PlayStation2 game entertainment system.

A multiplier-accumulator macro for a 45 MIPS embedded RISC processor

This paper describes a high speed and area effective multiplier-accumulator for an embedded RISC processor. The point is to utilize a multiplier array and the Booths encoder twice in a cycle. This multiplier-accumulator can execute one multiply-add operation (32bit multiplication followed by 64bit addition) per cycle at 50MHz. The area is 2.35mm2 with 0.4¿m CMOS technology.

A Design Methodology Realizing an Over GHz Synthesizable Streaming Processing Unit

A 7.07 mm2 synthesizable streaming processing unit (SPU) is fabricated in a 65 nm CMOS technology with 8 level copper layers. It is migrated from its original custom design to a synthesizable design to get higher design portability. New features are a new floor plan, height optimized standard cell library, local clock generator cloning and adaptive wire width control. Its logic area is 30% smaller than the full custom designed SPU in the same process generation. Correct functional operation is realized in 4 GHz at 1.4 V.

Super integration circuit device having a plurality of IC-chip equivalent regions formed on a single semiconductor substrate

At least first and second IC-chip equivalent regions having functions available from conventional one-chip IC device are formed on a single semiconductor substrate. An output of the second region is supplied to an input terminal of the first region. The output of the second region is also delivered at an external terminal in response to a test signal through a multiplexer or a bidirectional buffer.

Low-power consumption and low-voltage operation PLA (L/sup 2/-PLA) using 1.2 mu m double poly-silicon CMOS E/sup 2/PROM technology

By using a unique CMOS E/sup 2/PROM technology, a novel field PLA (programmable logic array) has been developed. Owing to very low power consumption and low-voltage operation the PLA (L/sup 2/-PLA) is suitable for most consumer usage. To achieve this performance a soft-write free E/sup 2/PROM, a new low-power sense amplifier and an input transition detector (ITD) are used. L/sup 2/-PLA can operate in a wide range of supply voltage (1.0 V to 6.0 V) and consumes only 8 mA and 1 MHz (5 V supply voltage). Moreover, it has a standby mode in which the current consumption is extremely low (below 1 mu A).<<ETX>>