Hiroaki Terada

Direct generation of data-driven program for stream-oriented processing

This paper proposes a scheme that directly transforms unified system specifications into highly parallel dynamic data-driven programs incrementally in an interactive fashion. In this paper the scheme proposed is described with special emphasis on its application to stream-oriented processing such as the multimedia signal processing. An abstract data type for generalized multiple data streams is introduced in order to facilitate interpretations of hierarchical and diagrammatic specifications. Also an optimization technique applicable in fitting the specifications to a specific hardware configuration is shown. Finally, practicability of the methodology is illustrated through a design process of an HDTV signal decoder.

Flow-Thru Processing concept and its application to soft-computing

Abstract This paper first presents a new system design paradigm by which unified functional specifications of a system are made possible by introducing data-driven interpretation of a set of multi-lateral graphical descriptions equally applicable for software and hardware portions of the system implementation. It is also presented that the software portions of the system specifications are directly convertible into executable target programs on data-driven processors without losing any structural features inherently built into the original system specifications. Then, the data-driven processors are shown to be realizable by a self-timed pipeline structure naturally suitable for ULSI realizations in terms of power consumption and latency tolerance. Therefore, if the hardware portions of the system are also implemented by the same self-timed configuration, it is possible to realize a seamless unification of the software and hardware functions of the system on a single chip. Finally some examples of system realization are presented with special emphasis on possible applications to soft-computing such as genetic algorithms.

A data-driven execution control scheme and its experimental study

The authors have proposed a high-level parallel processing system representing the data-drive principle (including history-sensitive processing by diagrammatical language) and have been investigating its realization. Realization of high-level processing by the data-driven principle requires a load and function distribution scheme to secure the smooth data flow corresponding to the input stream into the system. Together with the results of experiment, this paper describes a systematic control scheme for load and function distribution of the data-driven execution function through the construction of clusters adapted to the hierarchical diagrammatical program structure. In other words, the proposed system realizes the data-driven execution functions of the hierarchical system by an iterative structure composed of fundamental functions, namely input-output, function processing, history-sensitive processing and firing control. This paper first describes the load and function distribution scheme for the fundamental function in the data-driven execution control. Then, using an experimental system with common-bus multiprocessor structure, it is shown that the proposed system is useful in realizing high-level parallel processing. Lastly, based on the geometrical connection structure of the diagrammatical program, a semiquantitative guideline is presented for the distributed assignment of fundamental functions in the hierarchical cluster structure.

Super-Pipelined Implementation of IP Packet Classification

Abstract With developing all-optical communication networks, highly-functional and highspeed boundary routers and home gateways are becoming to be required. In this paper, high-speed pipelined algorithm for packet classification which is one of heavy load functions within boundary routers is proposed. Its software implementation scheme on a data-driven processor equipped with flexible capability of pipelined parallel processing is also discussed. Finally, it is shown at maximum performance exchanged for simulation and experimental hardware evaluation that the scheme achieves 12M IPv4 packets per second by only 6% additional hardware cost.