Hirokazu Yoshizawa

MOSFET-only switched-capacitor circuits in digital CMOS technology

Design techniques are described for the realization of precision high linearity switched-capacitor (SC) stages constructed entirely from MOS transistors. The proposed circuits use the gate-to-channel capacitance of MOSFETs for realizing all capacitors. As a result, they can be fabricated in any inexpensive basic digital CMOS technology, and the chip area occupied by the capacitors can be reduced. A number of different SC stages have been designed and fabricated using the proposed techniques. These included SC amplifiers, gain/loss stages, and data converters. Both the simulations and the experimental results obtained indicate that very high linearity (comparable to that achieved using analog fabrication processes with two poly-Si layers) can be achieved in these circuits using basic CMOS technology.

High-linearity switched-capacitor circuits in digital CMOS technology

A high-linearity switched-capacitor (SC) branch using MOSFET capacitors is presented. Simulation results for an SC voltage amplifier show the effectiveness of the branch and its capability to realize linear SC circuits with MOSFET capacitors.

Switched-Capacitor Track-and-Hold Amplifiers With Low Sensitivity to Op-Amp Imperfections

This paper describes high-precision switched-capacitor (SC) track-and-hold amplifier (THA) stages. They use a novel continuous-time correlated double sampling (CDS) scheme to desensitize the operation to amplifier imperfections. Unlike earlier predictive-CDS amplifiers, the circuits do not need a sampled-and-held input signal for their operation. During the tracking period, an auxiliary continuous-time signal path is established, which predicts the output voltage during the holding period. This allows accurate operation even for low amplifier gains and large offsets over a wide input frequency range. Extensive simulations were performed to compare the performance of the proposed THAs with earlier circuits utilizing CDS. The results verify that their operation is far more robust than that of any previously described SC amplifiers

MOSFET-only switched-capacitor circuits in digital CMOS technologies

Design techniques are described for high-linearity switched-capacitor (SC) stages constructed entirely from MOS transistors. The proposed circuits use the gate-to-channel capacitance of MOSFETs for realizing all capacitors. As a result, they can be fabricated in any inexpensive basic digital CMOS technology, and the chip area occupied by the capacitors is much reduced. A number of different SC stages have been designed and fabricated using the proposed techniques. These included SC amplifiers, gain/loss stages and data converters. Both the simulations and the experimental results obtained indicated that very high linearity can be achieved in these circuits.

A high-linearity low-voltage all-MOSFET delta-sigma modulator

The implementation of a second-order switched-capacitor delta-sigma modulator is described. The modulator uses MOSFETs in their accumulation region as capacitors, with the input branches linearized using series compensation. It utilizes only basic digital CMOS technology and was fabricated in a 1.2 /spl mu/m process. The chip area of the modulator is about 1 mm/sup 2/. Measured results show that the modulator has a 94 dB peak S/THD, a 96 dB peak S/N and an 86 dB peak S/THD+N for a 6 kHz bandwidth with 5.4 mW power dissipation using a 3 V power supply and a 3.6 V capacitor bias voltage.

A 101 dB DR 1.1 mW audio delta-sigma modulator with direct-charge-transfer adder and noise shaping enhancement

A low-power audio delta-sigma modulator (DSM) is presented. Two new techniques are proposed to reduce the overall power dissipation of the modulator: a power-efficient direct-charge-transfer adder is employed, and noise-shaping enhancement is implemented by feeding the differentiated quantization noise to the input of the second integrator. The measured power dissipation is 1.1 mW, the dynamic range is 101.3 dB, the spur-free dynamic range is 112 dB and the signal-to-noise-plus-distortion ratio is 99.3 dB. The power efficiency of this design is among the best in DSMs with high (over 15) ENOBs.

0.5-V 70-nW Rail-to-Rail Operational Amplifier Using a Cross-Coupled Output Stage

We develop and fabricate a 0.5-V rail-to-rail operational amplifier (op-amp) with ultralow-power operation in a 0.18-μm standard complementary metal-oxide-semiconductor process. The op-amp has a two-stage structure that comprises a complementary input stage and a novel cross-coupled output stage. The cross-coupled output stage increases the transconductances of the metal-oxide-semiconductor field-effect transistors of the output stage without requiring an additional chip area. Hence, it increases the gain of the op-amp and drivability for a capacitive load. Our experimental results showed that the dc gain was 77 dB at the common-mode input voltage of 0.25 V with a supply voltage of 0.5 V. DC gains of more than 40 dB were obtained for common-mode input voltages ranging 50-450 mV. Furthermore, the unity-gain frequency was 4.0 kHz and the phase margin was 56°, with a capacitive load of 40 pF. The power consumption was 70 nW, including all bias circuits.

Switched-capacitor track-and-hold amplifier with low sensitivity to op-amp imperfections

A novel track-and-hold amplifier stage is described. It relies on continuous-time correlated double sampling to make the operation insensitive to amplifier imperfections. Simulations indicate that the circuit functions well even if the amplifier gain and bandwidth are low

An improved figure-of-merit equation for op-amp evaluation

An improved figure-of-merit (FoM) equation is proposed for opamp evaluation. This equation has a modification factor to include the effect of the phase margin, which is not considered in a conventional FoM equation. Simulation results confirm that the proposed FoM equation drastically suppresses the effect of load capacitance variations. By using the proposed FoM equation, evaluations of op-amps become more reasonable as compared with the comparisons using the conventional FoM equation.

A 0.5-V 85-nW rail-to-rail operational amplifier with a cross-coupled output stage

A 0.5-V rail-to-rail operational amplifier (op-amp) with a large common-mode input range is proposed. It has a two-stage structure which consists of a complementary input stage and a novel cross-coupled output stage. The cross-coupled output stage increases the transconductances of MOSFETs of the output stage without increasing the chip area. And hence, it increases the drivability for a capacitive load. Using HSPICE simulations, it is verified that the proposed circuit has a DC gain of more than 80 dB for common-mode input voltages from 40 mV to 400 mV with a supply voltage of 0.5 V. Unity-gain frequency is 8.2 kHz with a capacitive load of 40 pF and the power consumption is 85nW including all bias circuits.