Hiroki I. Fujishiro

Enhancement-mode pseudomorphic inverted HEMT for low noise amplifier

Characteristics of the pseudomorphic inverted HEMT (P-I-HEMT) are compared with those of the pseudomorphic HEMT. Both devices were fabricated in enhancement mode by the same process. P-I-HEMT shows a higher maximum transconductance of 590 mS/mm, and higher K-value of 600 mS/Vmm at a threshold voltage of O V, and better pinch-off characteristics than its counterpart. Noise characteristics of P-I-HEMT are reported. Lower noise figure (1.0 dB at 18 GHz) was obtained in the P-I-HEMT. It is concluded that the P-I-HEMT shows far better noise characteristics than the other at low drain voltage and current. >

Modulation of Drain Current by Holes Generated by Impact Ionization in GaAs MESFET

A hole current generated by impact ionization in the channel at high drain voltages is measured using a GaAs MESFET with a conductive buried p layer (CBP-MESFET). The hole injection into the p layer beneath the channel is found to be the origin of the kink effect. A sidegating effect in the CBP-MESFET is also studied. A suppression of the sidegating effect by the negatively biased p layer is shown. An anomolous behavior in the sidegating effect at high drain voltages is observed; it may be related to the holes generated by impact ionization.

A Sub-10 ps/gate Direct-Coupled FET Logic Circuit with 0.2 µm-Gate GaAs MESFET

A 0.2 µm-gate buried p-layer metal semiconductor field-effect transistor (MESFET) using a new gate fabrication technique is reported. With this technique, the gate length can be easily reduced down to less than 0.2 µm. The source resistance of enhancement mode field-effect transistor (FET) can also be reduced, resulting in excellent DC and RF performance. The maximum transconductance of 648 mS/mm and K-value of 506 mS/V mm were obtained. The maximum cutoff frequency was as high as 96.1 GHz. The propagation delay time of 8.1 ps/gate was observed with a power dissipation of 1.7 mW/gate at a supply voltage of 1 V.

A 20-Gb/s flip-flop circuit using direct-coupled FET logic

A new type of direct-coupled FET logic (DCFL) flip-flop called the memory cell type flip-flop (MCFF) is presented. The MCFF operates faster than conventional DCFL flip-flops and enhances the DCFLs advantages, such as low power consumption and high packing density. A D-flip-flop IC and a 1/8 divider IC were developed using the MCFF. These ICs were fabricated using 0.2- mu m-gate pseudomorphic inverted HEMTs. The D-flip-flop IC is confirmed to operate up to 20 Gb/s. The 1/8 divider is toggled up to a maximum frequency of 25 GHz. These results prove that the MCFF enables DCFL circuits applicable not only to large-scale integration but to small-scale and medium-scale integration operating up to 20 Gb/s as well. >

Pseudomorphic inverted HEMT suitable to low supplied voltage application

An enhancement-mode pseudomorphic inverted HEMT with short gate length shows superior saturation properties at low drain voltage. Such saturation properties are suitable for low-supplied-voltage applications. High-frequency properties of FETs were also studied, using two types of frequency-dependent measurement systems which represent active load and common-source circuits. It was confirmed that low knee voltage in the static I-V curve is preserved above 100 kHz. The estimated output power for the device is 50% higher than that of conventional pseudomorphic HEMT at supplied voltage of 1 V. >

Sidegating Effects in Inverted AlGaAs/GaAs HEMT

Sidegating effects in submicron gate I-HEMTs are reported over a wide range of the drain voltage. A kink in the drain current and the disappearance of the sidegating effect at high drain voltages (3~4 V) are attributed to the hole injection caused by the impact ionization in the channel. The observation of a new type of sidegating effect at higher drain voltages (>4 V) is also reported. The strong drain voltage dependence is explained by the enhanced electron injection into the substrate caused by the higher hole injection.

Behavior of Ga atoms on Si(001) surface at high temperature

The growth processes and structures of Ga layers formed on a Si(001) surface have been studied by scanning tunneling microscopy and low-energy electron-diffraction analysis. Si(001) wafers cut at 0.5° toward the [110] direction and showing a double-domain surface structure were used as substrates. Ga atoms from a Knudsen cell were deposited on substrates maintained at 600°C. In a Ga coverage range between 0.15 and 0.30 monolayer (ML), a Si(001)2×3–Ga structure composed of Ga ad-dimers rows was formed. In this coverage range, the ratio of the surface area of the TA terrace to that of the TB terrace (terraces where Si dimer rows run parallel and perpendicular to the step, respectively) was changed by step rearrangement, and biatomic steps were formed partially. Such step rearrangement can be explained by the substitution of Si atoms by Ga atoms at kinks. On the TB terrace, Ga ad-dimer rows along the SA step filled the terrace, while those along the SB step (an SA step where Si dimer rows on the upper terrac...

Noise Analysis of GaAs-MESFETs by Physics-Based Circuit Simulator Employing Monte Carlo Technique

SUMMARY Noise characteristics of GaAs metal-semiconductor field effect transistors (GaAs-MESFETs) with scaled-down dimensions are analyzed and modeled using a physics-based circuit simulator employing the Monte Carlo (MC) particle technique. The microscopic dynamics of electrons is also analyzed to investigate the mechanism of noise generation in a channel. Noise spectral densities of GaAs-MESFETs with two different geometries are estimated by evaluating fluctuations in instantaneous terminal currents. Then, minimum noise figures, Fmin, and noise figure circles are estimated using the noise spectral densities and Y-parameters. Because of an increase in y21 and suppression of an increase of noise spectral density, the device with an n+-region extending to below the drain-side edge of the gate contact exhibits a smaller noise figure. Suppression of the electron velocity fluctuation caused by electron transitions to higher valleys in a high electric field region is responsible for the noise suppression.

Characterization of Ultrahigh-Speed Pseudomorphic InGaAs/AlGaAs Inverted High Electron Mobility Transistors

A detailed characterization of ultrahigh-speed pseudomorphic InGaAs/AlGaAs inverted high electron mobility transistors (pseudomorphic I-HEMTs) is reported. Charge control analysis indicates that the pseudomorphic I-HEMT accomplishes improved transconductance (gm) and reduced short channel effects due to higher concentration and excellent confinement of two-dimensional electron gas (2DEG) in the InGaAs channel. The 0.2 µm gate pseudomorphic I-HEMTs reported here exhibit superior DC and RF performances, i.e., maximum transconductance (gmmax) of 565 mS/mm, cutoff frequency (fT) of 110 GHz and propagation delay times (τpds) of 6.6 ps/gate at R.T. and 4.9 ps/gate at 120 K. Delay time analysis reveals the reduction of both the electron transit time (τtransit) and the channel charging time (τchannel) in the pseudomorphic I-HEMT, which are significant factors in the ultrahigh-speed performance. Higher electron saturation velocity (υs:2.1×107 cm/s) and improved gm are considered to contribute to the reduction in τtransit and τchannel.

Monte Carlo study of strain effect on high field electron transport in InAs and InSb

We calculate the unstrained and the strained band structures of InAs and InSb by means of the empirical pseudopotential method. The impact ionization threshold energy, Eth, is calculated while keeping the energy and momentum conservation. Then the electron transport in the unstrained and the strained InAs and InSb is investigated by using the Monte Carlo (MC) method. In both InAs and InSb, the average electron velocity, vd, increases monotonically with the electric field strength, f. The tensile strain makes the low field electron mobility, μ, higher, and vice versa, which is resulted from the dependence of the effective mass in the Γ valley, m||∗(Γ), on the strain. At the high f, many electrons are restricted within the bottom of the Γ valley because of losing most of their energy by the impact ionization, which results in keeping vd large at the high f. The tensile strain makes Eth smaller and then the impact ionization coefficient, α, larger, and vice versa. Consequently, vd at the high f becomes larger under the tensile strain and smaller under the compressive strain.