Hiroki Kawada

Metrology of LER: influence of line-edge roughness (LER) on transistor performance

The influence of line-edge roughness (LER) on transistor performance was investigated experimentally and the preciously proposed guideline for CD and LER measurements was examined. First, regarding the transistor-performance measurements, a shift of roll-off curves caused by LER within a gate pattern was observed. Moreover, the effect of transistor-width fluctuation originating from long-period LER was found to cause a variation in transistor performance. Second, regarding LER and CD metrology, the previously reported guideline was validated by using KrF and ArF resist-pattern samples. It was found that both CD and LER should be evaluated with the 2-μm-long inspection area. Based on this guideline, a comprehensive approach for evaluating LER and CD for transistor fabrication process is presented. The authors consider that this procedure can provide useful information for the 65-nm-node technology and beyond.

Characterization of line-edge roughness in resist patterns and estimations of its effect on device performance

A guideline for evaluating LER and total procedure to estimate effects of measured LER on device performance were proposed. Spatial-frequency distributions of LER in various resist materials were investigated and general characteristics of spatial-frequency distribution of LER were obtained. Measurement parameters for accurate LER measurement can be calculated according to the guideline. Measured line-width distribution was used for predicting degradation and variation in MOS transistor performance using the 2D device simulation. Effect of long-period component of LER was clarified as well as short-period component.

Bias-free measurement of LER/LWR with low damage by CD-SEM

We propose a new method for the evaluation of line-edge or linewidth roughness (LER/LWR). Conventional, directly measured LER/LWR values always contain a random noise contribution, which is called LER/LWR bias. Our method can separate this bias artifact from the true LER/LWR by using a single image of the sample pattern. The idea is based on the dependency of a measured LER/LWR value on the image-processing parameter for noise reduction. Both, the conventional and the new bias-free LER were calculated on series of images with different frame integration numbers but a fixed field of view. In addition, the validity of this method to the gate-LWR measurement on an ArF resist line pattern was examined. The LER/LWR obtained by our method was independent of the frame number, and agreed with the conventional LER/LWR as measured on an image with a sufficiently large frame-number. That is, our method can evaluate LER/LWR without random-noise contribution, suggesting that the method can be applied to images recorded under low-sample-damage conditions (i.e., low signal-to-noise ratio). It is concluded that the proposed bias-free LER/LWR measurement method will be a powerful tool in lithography metrology especially for achieving practical and accurate LER/LWR measurement with low sample damage.

Study of Measurement Condition Optimization in Critical Dimension-Scanning Electron Microscope

The critical-dimension scanning electron microscope (CD-SEM) is an essential tool for semiconductor fabrication process control because of its high resolution and high precision. However, in ArF lithography, the CD of resist changes during CD-SEM measurement due to shrinkage caused by the electron beam irradiation. This shrinkage can be reduced by measurement parameters; however, there is a trade-off relationship between shrinkage and precision. Thus, measuring the CD of an ArF resist pattern precisely with small shrinkage is difficult. The authors propose an optimization method using the Taguchi method. Four measurement parameters were chosen as control factors for an L18 orthogonal array: probe current, acceleration voltage, horizontal length of field-of-view, and number of image acquisitions. As a result, high prediction accuracy was obtained that is smaller than 0.2 nm for shrinkage and 0.1 nm for precision. Moreover, an optimum measurement condition that achieves 0.28 nm shrinkage and 0.37 nm precision was also obtained. Thus, the proposed method was demonstrated as a promising method to optimize CD measurement parameters.

Device-correlated metrology for overlay measurements

Abstract. One of the main issues with accuracy is the bias between the overlay (OVL) target and actual device OVL. In this study, we introduce the concept of device-correlated metrology (DCM), which is a systematic approach to quantify and overcome the bias between target-based OVL results and device OVL values. In order to systematically quantify the bias components between target and device, we introduce a new hybrid target integrating an optical OVL target with a device mimicking critical dimension scanning electron microscope (CD-SEM) target. The hybrid OVL target is designed to accurately represent the process influence on the actual device. In the general case, the CD-SEM can measure the bias between the target and device on the same layer after etch inspection (AEI) for all layers, the OVL between layers at AEI for most cases and after develop inspection for limited cases such as double-patterning layers. The results have shown that for the innovative process compatible hybrid targets the bias between the target and device is small, within the order of CD-SEM noise. Direct OVL measurements by CD-SEM show excellent correlation between CD-SEM and optical OVL measurements at certain conditions. This correlation helps verify the accuracy of the optical measurement results and is applicable for the imaging base OVL method using several target types advance imaging metrology, advance imaging metrology in die OVL, and the scatterometrybase OVL method. Future plans include broadening the hybrid target design to better mimic each layer process conditions such as pattern density. Additionally, for memory devices we are developing hybrid targets which enable other methods of accuracy verification.

Characterization of Line-Edge Roughness in Cu/Low-k Interconnect Pattern

To establish a method of measuring interconnect line-edge roughness (LER), low-k line patterns were observed and electric field concentration was simulated on the basis of observation results. Wedge-shaped LERs were observed at the edges of low-k lines, and the bottom and the top widths of the average wedge feature were 60 and 7 nm (or smaller), respectively. Simulation showed that LER causes serious electric field concentration, which may cause the degradation of time-dependent dielectric breakdown (TDDB) lifetime at 100-nm-pitch Cu/low-k interconnects. The maximum electric field strength depends on the conventional LER metric 3Rq, but depends more strongly on the wedge angle, the curvature of the tip. That is, other metrics such as wedge angle can predict fatal electric field concentration caused by LER than the conventional metric 3Rq.

A Discussion on How to Define the Tolerance for Line-Edge or Linewidth Roughness and Its Measurement Methodology

A metrological definition and a target value for linewidth roughness (LWR) in a gate pattern of MOSFETs are proposed. The effects of sampling interval gate-LWR measurements by critical-dimension scanning electron microscopy on measurement accuracy were examined by both experiment and simulation. It was found that a 10-nm interval is sufficiently small to fully characterize roughness in a typically chosen 2-mum-long line. Random image noise and intrinsic LWR variations are found to have larger effects on the measured LWR value than the finiteness of the sampling interval. A practical procedure for improving the measurement accuracy is also devised. Moreover, a methodology for establishing the gate-LWR target is proposed. Threshold-voltage shift caused by gate-LWR is determined from the LWR spectrum and the I-V curves of a transistor without LWR (i.e., ideal I-V curves).

Influence of electron incident angle distribution on CD-SEM linewidth measurements

The linewidth measurement ability of the Model-Based Library (MBL) matching technique is evaluated by a simulation study, and an improvement in the technique is proposed. In this study, a focused electron beam model is introduced in the MONSEL Monte Carlo simulator to estimate the effects of the electron incident angle distribution on linewidth measurements. By using the focused electron beam model, the images that will be obtained by an actual critical-dimension scanning electron microscope (CD-SEM) were simulated. Measurements were carried out on the images which would be taken with the SEM focus conditions in a range maintained by the auto-focus system. As a result of measurements of simulated images with various sample geometries, it was confirmed that the current MBL matching with a simple Gaussian electron beam model could cause a measurement error of more than 3 nm for the linewidth and 2° for the sidewall angle. Since the incident angle distribution distorts the effective beam shape and image profile at the edge of a pattern, conventional MBL matching with a simple Gaussian beam model cannot give a proper measurement of sample geometry for the image profile formed by the focused electron beam, and this results in measurement errors. To eliminate these measurement errors, another library produced by the focused electron beam model, is employed for the MBL matching. The new library consists of simulated profiles at only the best focus, and it enables the MBL to use a better model and to achieve accurate measurements without increased computational costs. By using the new library, measurement errors are reduced to 0.6nm for the linewidth and to 0.2° for the sidewall angle.

Hybrid metrology solution for 1X node technology

The accelerated pace of the semiconductor industry in recent years is putting a strain on existing dimensional metrology equipments (such as CDSEM, AFM, Scatterometry) to keep up with ever-increasing metrology challenges. However, a revolution appears to be forming with the recent advent of Hybrid Metrology (HM) - a practice of combining measurements from multiple equipment types in order to enable or improve measurement performance. In this paper we extend our previous work on HM to measure advanced 1X node layers - EUV and Negative Tone Develop (NTD) resist as well as 3D etch structures such as FinFETs. We study the issue of data quality and matching between toolsets involved in hybridization, and propose a unique optimization methodology to overcome these effects. We demonstrate measurement improvement for these advanced structures using HM by verifying the data with reference tools (AFM, XSEM, TEM). We also study enhanced OCD models for litho structures by modeling Line-edge roughness (LER) and validate its impact on profile accuracy. Finally, we investigate hybrid calibration of CDSEM to measure in-die resist line height by Pattern Top Roughness (PTR) methodology.

Characterization of line-edge roughness in Cu/low-k interconnect pattern

To establish a method for measuring interconnect line-edge roughness (LER), low-k line patterns were observed and electric-field concentration was simulated based on the observation results. Wedges were observed on the edges, and the bottom and the top widths of the average wedge feature were 60 nm and 7 nm (or smaller), respectively. Simulation showed that the LER causes serious degradation of TDDB immunity at 100-nm-pitch Cu/low-k interconnects. The maximum electric-field intensity depends upon the conventional LER metric, 3Rq, but depends more strongly on the wedge angle, the curvature of the tip, and the minimum linewidth.