Hiroki Sugano

Partially Parallel Architecture for AdaBoost-Based Detection With Haar-Like Features

This paper proposes a hardware architecture for object detection based on an AdaBoost learning algorithm with Haar-like features as weak classifiers. We analyze and discuss the parallelism in this detection algorithm and propose a partially parallel execution model suitable for hardware implementation. This parallel execution model exploits the cascade structure of classifiers, in which classifiers located near the beginning of the cascade are used more frequently than subsequent classifiers. We assign more resources to these earlier classifiers to execute in parallel than to subsequent classifiers. This dramatically improves the total processing speed without a great increase in circuit area. Moreover, the partially parallel execution model achieves flexible processing performance by adjusting the balance of parallel processing. In addition, we implement the proposed architecture on a Virtex-5 FPGA to show that it achieves real-time object detection at 30 fps on VGA video without candidate extraction.

Hardware Architecture for HOG Feature Extraction

Pedestrian recognition on embedded systems is a challenging problem since accurate recognition requires extensive computation. To achieve real-time pedestrian recognition on embedded systems, we propose hardware architecture suitable for HOG feature extraction, which is a popular method for high-accuracy pedestrian recognition. To reduce computational complexity toward efficient hardware architecture, this paper proposes several methods to simplify the computation of HOG feature extraction, such as conversion of the division, square root, arctangent to more simple operations. To show that such simplifications do not spoil the recognition accuracy, the detection performance is also evaluated using a support vector machine. Moreover, we implement the proposed architecture on an ALTERA Stratix II FPGA using Verilog HDL to evaluate the circuit size and the processing performance of the proposed architecture. Implementation results show that real-time processing for 30 fps VGA video can be achieved if 10 instances of the proposed hardware are used in parallel.

A Specialized Processor Suitable for AdaBoost-Based Detection with Haar-like Features

Robust and rapid object detection is one of the great challenges in the field of computer vision. This paper proposes a hardware architecture suitable for object detection by Viola and Jones based on an AdaBoost learning algorithm with Haar-like features as weak classifiers. Our architecture realizes rapid and robust detection with two major features: hybrid parallel execution and an image scaling method. The first exploits the cascade structure of classifiers, in which classifiers located near the beginning of the cascade are used more frequently than subsequent classifiers. We assign more resources to the former classifiers to execute in parallel than subsequent classifiers. This dramatically improves the total processing speed without a great increase in circuit area. The second feature is a method of scaling input images instead of scaling classifiers. This increases the efficiency of hardware implementation while retaining a high detection rate. In addition we implement the proposed architecture on a Virtex-5 FPGA to show that it achieves real-time object detection at 30 frames per second on VGA video.

A real-time object recognition system on cell broadband engine

Accurate object recognition based on image processing is required in embedded applications, where real-time processing is expected to incorporate accurate recognition. To achieve accurate real-time object recognition, an accurate recognition algorithm that can be quickened by parallel implementation and a processing system that can execute such algorithms in real-time are necessary. In this paper, we implemented an accurate recognition scheme in parallel that consists of boosting-based detection and histogram-based tracking on a Cell Broadband Engine (Cell), one of the latest high performance embedded processors. We show that the Cell can achieve real-time object recognition on QVGA video at 22 fps with three targets and 18 fps with eight targets. Furthermore, we constructed a real-time object recognition system using SONYR® Playstation 3, one of the most widely used Cell platforms, and demonstrated face recognition with it.

Parallel implementation of pedestrian tracking using multiple cues on GPGPU

Nowadays, pedestrian recognition for automotive and security applications that require accurate recognition in images taken from distant observation points is a recent challenging problem in the field of computer vision. To achieve accurate recognition, both detection and tracking must be precise. For detection, some excellent schemes suitable for pedestrian recognition from distant observation points are proposed, however, no tracking schemes can achieve sufficient performance. To construct an accurate tracking scheme suitable for pedestrian recognition from distant observation points, we propose a novel pedestrian tracking scheme using multiple cues: HSV histogram and a HOG feature. Experimental results show that the proposed scheme can properly track a target pedestrian where existing schemes fail. Moreover, we implement the proposed scheme on NVIDIA Tesla C1060 processor, one of the latest GPGPU, to achieve real-time processing of the proposed scheme. Experimental results show that computation time required for tracking of a frame by our implementation is reduced to 13.8 ms even though Intel(R) Core(TM) i7 CPU 965 @ 3.20GHz spends 122.0 ms.

Parallel implementation of morphological processing on Cell/BE with OpenCV interface

One of the most frequently used operations in image recognition is morphological processing. In this paper, we propose a parallel implementation of morphological processing optimized for cell broadband engine (cell), which is one of the latest high performance embedded processors. By utilizing the computational power of cell suitable for image recognition, we achieve high-speed morphological processing. Moreover, we construct a software interface to the parallel implemented morphological operations on cell compatible with OpenCV library. By our implementation, two 3.6 GHz SPEs on cell can process erosion of a 1024times768 pixel image by a 5times5 pixel rectangle kernel in 0.601 milliseconds, though a 2.66 GHz Intel Core 2 processor takes 11.590 milliseconds to process it.

Highly optimized implementation of OpenCV for the Cell Broadband Engine

Recently, real-time processing of image recognition is required for embedded applications such as automotive applications, robotics, entertainment, and so on. To realize real-time processing of image recognition on such systems we need optimized libraries for embedded processors. OpenCV is one of the most widely used libraries for computer vision applications and has many functions optimized for Intel processors, but no function is optimized for embedded processors. We present a parallel implementation of OpenCV library on the Cell Broadband Engine (Cell), which is one of the most widely used high performance embedded processors. Experimental result shows that most of the functions optimized for the Cell processor are faster than functions optimized for Intel Core 2 Duo E6850 3.00GHz.

Parallel implementation of morphological processing by arbitrary kernels on Cell/BE with OpenCV interface

One of the most frequently used operations in image recognition is morphological processing. In this paper, we propose a parallel implementation of morphological processing optimized for Cell Broadband Engine (Cell), which is one of the latest high performance embedded processors. By utilizing the computational power of Cell suitable for image recognition, we achieve high-speed morphological processing. Moreover, we construct a software interface to the parallel implemented morphological operations on Cell compatible with OpenCV library. By our implementation, six 3.6 GHz SPEs on Cell can process erosion of a 640times480 pixel image by a 5times5 pixel elliptic kernel in 0.263 milliseconds, though a 2.66 GHz Intel Core 2 processor takes 0.547 milliseconds to process it under Intel Integrated Performance Primitives.

Pedestrian recognition in far-infrared images by combining boosting-based detection and skeleton-based stochastic tracking

Nowadays, pedestrian recognition in far-infrared images toward realizing a night vision system becomes a hot topic. However, sufficient performance could not be achieved by conventional schemes for pedestrian recognition in far-infrared images. Since the properties of far-infrared images are different from visible images, it is not known what kind of scheme is suitable for pedestrian recognition in far-infrared images. In this paper, a novel pedestrian recognition scheme combining boosting-based detection and skeleton-based stochastic tracking suitable for recognition in far-infrared images is proposed. Experimental results by using far-infrared sequences show the proposed scheme achieves highly accurate pedestrian recognition by combining accurate detection with few false positives and accurate tracking.

Opencv implementation optimized for a cell broadband engine processor

Recently, real-time processing of image recognition is required for embedded applications such as automotive applications, robotics, entertainment, and so on. OpenCV library is one of the most widely used libraries in image processing. Parallel implementation of OpenCV library on Cell Broad-band Engine (Cell), which is one of the most widely used high performance embedded processors, is shown in this paper. Experimental result shows that most of the functions optimized for Cell processor are faster than those optimized for Intel Core 2 Duo E6850 3.00 GHz.