Hironobu Niijima

Electron beam tester integrated into a VLSI tester

An integrated EB (electron-beam) testing system is constructed for precise failure analysis and reduction of total testing time, coupling a VLSI tester and an EB tester. Unique features of the system are briefly described, together with its system configuration and functions. The close connection of LSI testing and EB testing environments is further continued. It is planned to improve the integrated system to enable a simultaneous display of EB testing data in the LSI testing environment, with which it becomes possible to superimpose the EB pin data into the timing chart of normal pin data in the LSI testing. This type of connection of two environments is quite powerful and will be used in a standard testing method.<<ETX>>

New approach to integrate LSI design databases with e-beam tester

An integrated electron-beam tester is described. A set of novel computer-aided-verification tools based on a new software architecture has been implemented. It is closely coupled with industry-proven, high-performance e-beam hardware and CAD (computer-aided-design) databases. This results in a high throughput environment, allowing VLSI designers to debug their chips much more efficiently than with conventional approaches. These tools have a lower data preprocessing time, which is achieved by direct conversion of user databases, a higher run-time performance due to the application of the new architecture, and a lower disk storage usage.<<ETX>>

Scan design oriented test technique for VLSI's using ATE

A new test technique to localize failures of devices with scan design easily and quickly using LSI tester is proposed. This technique allows device designers or test engineers to localize the scan Flip Flops that failed using expressions based on the scan design of the device. These devices are defined by the Boundary Scan Description Language (BSDL) or an extension to BSDL proposed in this paper. This technique can be applied to standard boundary scan designs and to ad-hoc internal scan implementations. Furthermore, restrictions from limited tester resources has been solved by technique. As a result, it is possible to speed-up of the failure analysis resulting in a decrease of the test costs.

CAD driven high precision E-beam positioning

To shorten the silicon debugging time of VLSI chips with design rules of 0.5 /spl mu/ or less, an E-beam prober becomes an indispensable tool. However, the accuracy of E-beam positioning has to be greatly improved to the 0.1 /spl mu/ level so the best waveform can be acquired. To achieve such high precision, we use image processing techniques to do pattern matching between the CAD layout database and the SEM image. We will discuss the methods to filter and segment the SEM image, the methods to do the registration between the CAD layout database and the SEM image, and the method for final beam positioning on the SEM image. We will also reveal some test results.<<ETX>>