Hiroshi Iwata
Nara Institute of Science and Technology
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Publication
Featured researches published by Hiroshi Iwata.
european test symposium | 2010
Michiko Inoue; Akira Taketani; Tomokazu Yoneda; Hiroshi Iwata; Hideo Fujiwara
Timing-aware ATPGs are being developed to detect small delay faults for high defect coverage for current nanometer VLSI design. However, it results in a large test set compared with test generation targeting traditional fault models. This paper proposes a method to get a limited size of test set with high delay test quality based on statistical delay quality level (SDQL).
symposium/workshop on electronic design, test and applications | 2010
Hiroshi Iwata; Satoshi Ohtake; Hideo Fujiwara
Information on false paths is useful for design and test. Since identification of false paths at gate level is hard, several methods using high-level design information have been proposed. These methods are effective only if the correspondence between paths at register transfer level (RTL) and at gate level can be established. Until now, the correspondence has been established only by some restricted logic synthesis. In this paper, we propose a method for mapping RTL false paths to their corresponding gate level paths without such a specific logic synthesis.
design and diagnostics of electronic circuits and systems | 2010
Satoshi Ohtake; Hiroshi Iwata; Hideo Fujiwara
This paper proposes a new synthesis method for propagating information of paths from register transfer level (RTL) to gate level. The method enables false path identification at RTL without not only enforcing strong constraints on logic synthesis but also loss of the information about false paths identified. Experiments show that the proposed method can reduce hardware and timing overhead and improve propagability of false path information through logic synthesis compared with the previous methods.
asian test symposium | 2010
Hiroshi Iwata; Satoshi Ohtake; Michiko Inoue; Hideo Fujiwara
A globally-asynchronous and locally-synchronous (GALS) system has been known as a realistic hardware design solution for many difficulties such as global clock network that arise due to the continuous scaling of semiconductor technology. Although a full scan design method for synchronous circuits is applied to asynchronous circuits to achieve the same testability of their combinational parts, the overhead is extremely high. To reduce the overhead, several full scan design methods have been proposed but they cannot guarantee complete test. In this paper, we propose a bipartite full scan design as a new DFT method for asynchronous circuit where we guarantee complete test for both combinational and sequential parts of circuits with area and performance overhead comparable to the previous best method in terms of overhead.
Archive | 2009
Hiroshi Iwata; Satoshi Ohtake; Hideo Fujiwara
Archive | 2012
Satoshi Ohtake; Hiroshi Iwata; Michiko Inoue
IEICE Transactions on Information and Systems | 2017
Hiroshi Iwata; Nanami Katayama; Ken'ichi Yamaguchi
IEICE technical report. Dependable computing | 2014
Meguru Komatsu; Hiroshi Iwata; Ken'ich Yamaguchi
情報科学技術フォーラム講演論文集 | 2013
Shin'ya Ueoka; Hiroshi Iwata; Ken'ichi Yamaguchi
IEICE Transactions on Information and Systems | 2010
Hiroshi Iwata; Satoshi Ohtake; Hideo Fujiwara