Hiroshi Sukegawa
Toshiba
Network
Latest external collaboration on country level. Dive into details by clicking on the dots.
Publication
Featured researches published by Hiroshi Sukegawa.
international solid-state circuits conference | 2011
Daisaburo Takashima; Mitsuhiro Noguchi; Noboru Shibata; Kazushige Kanda; Hiroshi Sukegawa; Shuso Fujii
An embedded DRAM using a standard NAND flash memory process has been demonstrated for the first time. This embedded DRAM without extra costly manufacturing process realizes 2.4 mm2 /Mb macro density and provides large-capacity on-chip page buffers and data caches for NAND flash memories to enhance their performances. A 32 KB DRAM buffer macro with 1.5 μm2cell has been fabricated with a 32 nm NAND flash memory process. Even with small 3 fF cell using a planar MOS capacitor, an enough ±100 mV cell signal has been obtained by introducing a technique to self-boost cell node up to 4 V using a merit of high-voltage NAND flash process, and two techniques to curtail parasitic bitline capacitance down to 60 fF at 128 wordlines per bitline. An undershoot problem of cell nodes due to unwanted plateline bounce is resolved by a two-step-rise/fall wordline scheme. Installation of dummy cell scheme to obtain a half of “1” data (not an average of “1” and “0” data) cuts out 32 KB macro size by 1.3% while suppressing mismatch to 3 mV at the grounded bitline precharge. The 32 KB test vehicle shows 90 ns random cycle time with 15 ns burst cycle time (66 Mb/s/pin). The measured characteristics of 2 × 10-18 bit error rater (BER) by soft error and 10 ms data retention at 85 °C are enough for page buffer application in a NAND flash memory. The measured active current of 32 KB macro is 7 mA at 90 ns random cycle, but only 3.2 mA at practical use of 15 ns burst with 256B page access.
The Journal of The Institute of Image Information and Television Engineers | 2003
Akio Okazaki; Toshio Sato; Kentaro Yokoi; Hiroshi Sukegawa; Jun Ogata; Sadakazu Watanabe
An access control system that automatically logs in a user by his or her facial information is described. Furthermore, a method for automatically tracking logged data, based on a repetitive operation of template improvements, is shown. Face recognition is a favorable variety of biometrics for personal identification because users facial images can be captured successively from a standard video camera at a distance. Two models of the system using face recognition were tested to prevent fraud and to create automatic registration. Experimental results for a six-month test showed that the tracking capability of the method is quite practicable; the equal error rate for false rejection and false acceptance (EER) is only about one percent.
Archive | 1995
Hiroshi Sukegawa; Yasunori Maki; Takashi Inagaki
Archive | 1999
Hiroshi Sukegawa
Archive | 2002
Hiroshi Sukegawa; Kentaro Yokoi; Hironori Dobashi; Jun Ogata; Toshio Sato; Akio Okazaki
Archive | 2007
Masaki Fujiu; Noboru Shibata; Hiroshi Sukegawa
Archive | 1996
Hiroshi Sukegawa
Archive | 1995
Hiroshi Sukegawa
Archive | 2002
Toshio Sato; Akio Okazaki; Hiroshi Sukegawa; Jun Ogata
Archive | 2004
Hiroshi Sukegawa