Hiroshi Yamashita

Resolution analysis in electron‐beam cell projection lithography system

We have experimentally analyzed the resolution in electron‐beam cell projection lithography systems. The results indicated that the Coulomb interaction effect and the proximity effect are critical issues for resolution because of the larger beam current compared with the conventional variable‐shaped beam. We achieved a practical resolution of 0.18 μm, which is enough for 1 Gbit dynamic random access memory (DRAM) fabrication, by adjusting the beam current. We have also found that there is some interaction between the individual line beams (streams). Also, the beam profile degradation in cell projection lithography systems depends not only on the beam current but also on the distance between the streams. Therefore, in order to obtain higher resolution, these effects must be considered more carefully than in the case of conventional variable‐shaped beam lithography systems. A resolution of less than 0.15 μm, which is required for Gbit level DRAM fabrication, can then be available in cell projection lithogra...

Highly accurate critical dimension measurement for sub‐0.5‐μm devices

In the measurement of patterned resists, deviation of the critical dimension (CD) is frequently observed. We have found that contamination on the resist on a Si wafer can degrade the static repeatability more than the charging phenomenon at low accelerating voltage (Vacc), that is, near 1 kV. We investigate the dependence of contamination rate (Rc) and the normalized yield of secondary electrons (δ’) on Vacc and emission current (Ie) in order to clarify the influence of the contamination and charging effects. Experimental results indicate that we can minimize the Rc by optimizing Vacc and Ie. The Rc change cannot be attributed only to the contamination and charging effects, however. It seems, instead, that two competitive reactions (deposition and etching) occur simultaneously during the measurement at low voltage. The etching effect can be interpreted as a dissociation reaction at the resist surface. To reduce the CD deviation and improve the accuracy of the CD measurement, the accelerating voltage and c...

Subfield distortion of an EPL stencil mask

EPL (Electron Projection Lithography) is one of viable candidates for the NGL (Next Generation Lithography) used for the 65nm technology node and below. EPL uses the membrane mask with grillage structure to reinforce the membrane area. The NGL poses stringent requirements to mask accuracy. The most severe problem of membrane mask is IP (Image Placement) accuracy. In this study, distortion characteristics of an EPL stencil mask are analyzed by FEM (Finite Element Method). Its dependence on the grillage structure and the distribution of pattern density is presented. The distortion of the wet-etched wide grillage is negligible compared to the required IP accuracy. However, the distortion of the dry-etched narrow grillage cannot be negligible, which exceeds 5nm. The accumulation of the distortion will deteriorate the IP accuracy. The non-uniform distribution causes much larger distortion in membrane than the uniform one, which is quite unacceptable for the 65nm technology node and below. Improvement of the IP accuracy by the correction using an EPL optical system is also evaluated. The EPL optical system can reduce the distortion caused by the uniform distribution. However, the large distortion caused by the non-uniform distribution cannot be corrected. EPL requires its own design rules regulating the distribution of pattern density from the view point of IP accuracy.

Defect printability analysis on electron projection lithography with diamond stencil reticle

Mask defect printability of electron projection lithography (EPL) by using a diamond reticle with programmed defect pattern was investigated. Th reticle was obtained from NTT- AT and wafer exposure was performed by Nikons EB projection experimental column. In general, the printability of the defects of dot categories are lower than shift categories and the allowable defect size of dot categories in 70 nm node are larger than 100 nm on mask with +/- 10 percent critical dimension (CD) tolerance criteria except edge extension defect. On the other hand, the printability of the defects of shift categories is higher than dot categories. According to the defects CD dat of mask and resist patterns, CD error or placement error caused by the defects of shift categories show a linear correlation between the defect size of mask x reduction ratio and printed defect size of resist pattern. SO the allowable defect size of shift categories in 70 nm node should be less than 28 nm on mask.

Dynamic image placement accuracy of a stencil mask

Stencil masks are preferable for EPL (Electron-beam Projection Lithography)from the view point of resolution because it s free from the chromatic aberration caused by the electron energy loss in continuous membrane. However, its mechanical structure poses several concerns. Dynamic image placement (IP)accuracy is one of the essential concerns because patterns on the stencil mask are defined by free-standing Si structures. Moreover the whole pattern areas are supported by fine Si grid structures. The step-and-scan motion of EPL tools is expected to cause dynamic displacements of these fragile structures, which lead to deterioration of resolution, critical dimension (CD)and overlay (OL) accuracies. Two kinds of the dynamic displacements on an EPL stencil mask were estimated by simulations. One is the vibration of the free-standing structures and the other is the dynamic distortion of the whole pattern area. The maximum acceleration of 5 G was assumed in the simulations according to a throughput estimation. The free-standing structures are modeled into cantilever beams and both-end-fixed beams. It was found that the vibration of the structures could be suppressed below the amplitude of 1 nm by limiting the beam length. The limitations were practical ones for complementary split of mask layout. The whole pattern area was modeled into a simple grid structure. It was found that the maximum dynamic displacement was less than 7 nm. The OL accuracy was estimated including those dynamic displacements down to 35 nm node. The results show that the dynamic displacements of the EPL stencil masks would little affect the OL accuracy. The stencil mask is applicable for device fabrication at 70 nm node and below.

Rigorous simulation of statistical electron-electron interactions with fast multipole acceleration and a network of workstations

Rigorous simulation, which in concept is nearly linear in CPU time with microampere beam currents, has been developed for analyzing statistical electron–electron interactions in lens free regions joined by ideal lenses and apertures. The simulation method is based on combining fast multipole acceleration (FMA) with modifications to a message passing interface for use on a multiprocessor and on a network of workstations. As test cases, the distribution of scattered electrons versus deviation from focus is given as well as results for the interaction between simultaneously imaged spots. The performance improvement per level of spatial division was only about a factor of 2 instead of the expected factor of 8 due to the pencil shape nature of the beam. A FMA method that is adaptable to beam density and geometry is needed. It is projected that it will be possible to simulate a 30 μA beam current on a quad-Pentium Pro machine in half a day and in matter of hour on a network of workstations.

A Hybrid E-Beam/Deep-Uv Lithography For Gaas Fet's

A hybrid e-beam/deep-UV lithography (a D2ED process) and its application for GaAs FETs are described. A D2 ED process consists of Deep UV exposure and Development in MIBK (methyl isobutyl ketone) for less critical features, and E-beam exposure and Development in IPA (isopropyl alcohol) for critical fine features. E-beam exposure is performed at one pixel per minimum linewidth. A higher throughput and better linewidth control are obtained by using a D ED process. A high overlay accuracy is obtained by use of tungsten registration marks and D2ED processes for the source/drain and gate levels in GaAs FETs.

Sub-100nm pattern fabrication in e-beam lithography

Sub-100nm patterns have been fabricated in thick PMMA film on thick silicon substrates at low beam voltages using commercial e-beam machines. A higher contrast and an improved resolution are obtained by using an IPA development. 50-100nm lines are fabricated in 0.5- 1.0μm PMMA film on silicon substrates with 20-25kV e-beams. Practical aspects of sub-100nm pattern fabrication have been estimated. Pattern accuracy, field butting error, and overlay accuracy are better than ±0.1 μm 3 sigma.

Characterization of diazo‐type photoresists using e‐beam exposure and metal–ion‐free developers

The performance characteristics of diazo‐type positive photoresists are explored using e‐beam exposure and metal–ion‐free developers. For Tokyo Ohka OFPR1000, resist profiles with straight sidewalls are obtained while maintaining sufficient resist thickness. The effects of prebake and developer temperature on the solubility rate of OFPR1000 are investigated. A higher contrast is obtained with the resist prebaked at 65u2009°C and developed at 23u2009°C. Higher prebake temperatures and lower or higher developer temperatures result in a lower contrast. Submicron resolution can be obtained.