Hirotaka Komoda

Optical Beam Induced Current Techniques for Failure Analysis of Very Large Scale Integrated Circuits Devices

In failure analysis of complementary metal oxide semiconductor (CMOS) very large scale integrated (VLSI) circuits using optical beam induced current (OBIC) techniques, circuit analysis was carried out by studying the flow path of detected photocurrents for the first time. This circuit analysis revealed that the OBIC current can be detected even on a good unit. Furthermore, this gave a clear explanation as to the reason why the suspected failure site detected by OBIC and emission microscopy analyses did not always occur at the same site as the defect. This study showed that there is a high possibility of detecting a failure due to metal-metal short by OBIC analysis.

DETECTION OF OPEN CONTACT USING OPTICAL-BEAM-INDUCED CURRENT TECHNIQUES

Optical-beam-induced current (OBIC) techniques have been reported as very useful failure analysis tools for detecting leakage sites and latch-up sensitivity. In this study, this OBIC technique was successfully applied to detect an open contact site. Focused ion beam (FIB) cross-sectioning and observation of the open contact revealed the cause of open failure. This OBIC technique was proven to be very rapid and convenient, because no special sample preparation is necessary.

Novel charge neutralization techniques applicable to wide current range of FIB processing in FIB-SEM combined system

FIB-induced charging is one of the most critical issues for achieving successful circuit modifications of LSI. We have developed novel charge neutralization techniques applicable to a wide current range (from pico to nanoampere-order) of FIB processing in a FIB-SEM combined system. The method utilizes a 500 eV focused electron beam instead of an electron shower, and also a combination of microprobing and FIB-assisted deposition to make a current path from FIB processing point to the grounded microprobe. The effects of our techniques on charge neutralization capability were investigated using electrically erasable-programmable read-only memory devices and n-MOS transistors. For the low FIB current condition of less than 500 pA, it is found that the focused electron beam prevents threshold voltage shifts of both irradiated and neighboring transistors, and that the ratio of electron to ion beam currents is a key parameter to achieving effective charge neutralization. We also demonstrated that the combined method of microprobing and FIB-assisted deposition prevents parameter shifts of transistors even for high-current (nanoampere-order) FIB irradiation. Moreover, we evaluated the upper-limit resistance of the current path formed by FIB-assisted carbon deposition to prevent charging induced by a given FIB current.

Charge Neutralization Using Focused 500 eV Electron Beam in Focused Ion Beam System

We have proposed a technique for novel charge neutralization in a focused ion beam (FIB) system. To neutralize positive charges induced by FIB, this technique utilizes a focused 500 eV electron beam instead of an electron shower that often causes negative charges in a broad area around the FIB-irradiated point. We used erasable-programmable read-only memory devices to monitor surface charges. The results showed that the focused electron beam is effective for charge neutralization and prevented threshold voltage shifts of both irradiated and neighboring transistors. We also found that the ratio of electron to ion beam currents is a key parameter to achieving effective charge neutralization.

An example of fault site localization on a 0.18 μm CMOS device with combination of front and backside techniques

Abstract This paper describes a failure analysis on a 0.18 μm CMOS device. To find out fault mechanism, combination of several fault localization techniques that are both front and backside were utilized. Fault mechanism is discussed, including the relation between the results of these techniques and physical layout with circuit information. In this case, the failure device had these features: multi-metallization process with dummy fill metals, low supply voltage, and non-function with high IDD leakage. These features made verifying the fault mechanism very difficult. We provide an approach of voltage contrast method with FIB milling techniques. This approach enabled to probe inner nodes in the multi-metallization device and to verify the fault mechanism. We also discuss the verification with circuit simulation and the root cause in detail.

In Situ Focused Ion Beam (FIB) Observation of Al Electromigration

A new method for obtaining real-time monitoring of stressed interconnects has been discovered. This technique uses the focused ion beam (FIB) system. Under a stress of 3 MA/cm2 at 473 K, voids grown at a triple point occurred in Al-1.0%Si interconnects, and hillocks formed, as is seen during in situ observation of the aluminum microstructure. Since this study is theoretical, additional observation and study of the electromigration phenomenon using in situ monitoring is recommended.

Antistatic Technique for Suppressing Charging in Focused Ion Beam Systems Using Microprobing and Ion-Beam-Assisted Deposition

We have developed a novel antistatic technique for suppressing focused ion beam (FIB)-induced charging in a combined system of an FIB and a scanning electron microscope. Microprobing and FIB-assisted carbon deposition are utilized to make a current path through which FIB-induced positive charges flow to ground. The effects of our method on charge neutralization capability were investigated by measuring parameter shifts of n-channel metal–oxide–semiconductor transistors. The results showed that our method prevents parameter shifts of transistors even for high-current (nanoampere-order) FIB irradiation. We also evaluated the upper-limit resistance of the current path formed by FIB-assisted carbon deposition to prevent charging induced by a given FIB current.

Selective Excitation of a Symmetric Interference Plasmon Mode in Two Close Planar SiO2/Si Interfaces Observed by Electron Energy-Loss Spectroscopy

We have studied the effects of the SiO2/Si interface parallel to an electron beam on transmission electron energy-loss spectra of a SiO2 area for poly-Si/SiO2/Si samples. The dependence of the energy-loss spectra on the distance from the interface to the probe position and on the distance between two interfaces was investigated. Spectra obtained from the center of the thick (150 nm) SiO2 layer had no peak in the energy region of 4–10 eV. However, a peak at about 7 eV was observed in the spectra obtained at a position of 7.5 nm from the SiO2/Si interface for the same specimen. This peak was assigned to a SiO2/Si interface plasmon excitation. For the thin (15 nm) oxide poly-Si/SiO2/Si sample, on the other hand, the peak appeared at 8.7 eV. Furthermore, this peak shifts to higher energies as the oxide thickness decreases. This peak was assigned to an excitation of a symmetric interference plasmon mode in two close planar SiO2/Si interfaces.

Via high resistance failure analysis of LSI devices induced by multiple factors related to process and design

Abstract We investigated the root cause of a via high resistance issue due to fabrication process variations and mismatching design rule. Physical analyses of localized chip area including a failed via were first performed using cross-sectional TEM-EDX, EBSP and CL methods. These analyses results revealed the root causes as the formation of a Ti x Al y layer, porous and small void areas around the failed via bottom due to poor step coverage of the TiN/Ti barrier layer and the growth of the voids by tensile residual-stress in Al line. Next, to improve design rule, the dependencies of failure sites on cell structure and layout were evaluated by design analysis of the whole chip area. To realize this analysis, we developed a simple SEM observation method of the Ti x Al y layer using a combination of polishing and RIE techniques. This analysis result indicated the via high resistance issue tends to occur at only VIA1 of high-driver cells that have many fan-outs. From these combined analyses regarding fabrication and design, we found that METAL1 layout and the location of the VIA1 on METAL1 influence Ti x Al y and voids formation. In other words, metal line design rule is related strongly to this via high resistance issue.

Decapsulation technique using electrochemical etching for failure analysis of WLCSP n-type Si assembled module devices

Abstract Module devices consist of many electronic components mounted on a glass epoxy resin substrate. In failure analysis of the module device, it is necessary to expose the electronic components while maintaining these full functions. We have developed an electrochemical etching technique to decapsulate the overcoated anhydride cured epoxy resin. The method utilizes KOH alkali solution with DC bias voltage applied to a wafer level chip size package (WLCSP) n-type Si device. The DC bias acts as an electrical-etch-stopper of the n-type Si device’s substrate during the decapsulation of the overcoated resin. The efficiency and effectiveness of our decapsulation technique were evaluated using a Li ion/polymer protector module device. The mechanism of the electrochemical etching is also discussed.