Hirotoshi Shirasu

A single-chip CMOS filter/codec

A second generation LSI codec has been implemented. In this chip, switched-capacitor filters, a charge redistribution encoder and decoder, voltage references, a signaling logic circuit, and all necessary functions for voice-PCM conversion are integrated. The authors describe the codec and summarizes its characteristics.

A CMOS switched-capacitor variable line equalizer

The authors describe the design concept and experimental results for a CMOS switched-capacitor variable-line equalizer to be used in time-compression multiplexed (TCM) digital subscriber loop transmission systems. The equalizer transfer function is optimized in the time domain to relax the filter complexity to half that required by the application of classical communication techniques. In order the equalize wide-bandwidth high-speed digital data, a 50 MHz CMOS operational amplifier is proposed. The amplifier uses a folded cascade and buffer structure to achieve good stability against load capacitance change. An experimental chip has been fabricated with 2.5 /spl mu/m CMOS technology. The chip shows excellent characteristics for the equalization of 200 kb/s data travelling through pair cables of 5 km and 0.4 mm diameter.

An interpolative PCM CODEC with multiplexed digital filters

An LSI CODEC, an LSI multiplexed digital filter, and an LSI compandor are developed for telephone PCM AD/DA conversion. The total chip count is 1.56 chips per channel. The single-chip interpolative CODEC operates at a 32 kHz sampling rate with a 12-bit linear code input/output, and is implemented in a phosphorus buried emitter IIL process without the need for component value trimming. The digital filter is four-channel multiplexed for both transmitting and receiving directions. It is compactly fabricated with a combinatorial configuration in a 5 /spl mu/m NMOS process. A new word length extension technique was devised to realize an 87 dB dynamic range with the digital filter. The compandor, also fabricated in 5 /spl mu/m NMOS, is 16-channel multiplexed for both directions. All measured characteristics meet CCITT recommendations with sufficient margins. They demonstrate the inherent stability and noise immunity that can be achieved with the interpolation technique of the CODEC and the digital signal processing of the digital filter.

A CMOS SLIC with an automatic balancing hybrid

A CMOS subscriber line interface circuit (SLIC) that has an automatic balancing hybrid facility is presented. Some of the key system aspects of line interface circuits, such as the relation between zero-loss switching and an automatic balancing hybrid circuit, power dissipation in the line circuit, and foreign voltage protection are described first. Next, details of the SLIC LSI, which comprises a dial pulse detecting circuit and and automatic balancing hybrid circuit, are described. The LSI is implemented with CMOS switched capacitor technology and is mounted on a 20-in DIL.