Hiroyuki Ohshima

Future trends for TFT integrated circuits on glass substrates

The current status and the future trends of thin-film-transistor (TFT) integrated circuits are discussed following a review of their features. TFT devices have been applied to liquid-crystal displays and linear image sensors, both of which incorporate internally integrated driver circuits. From the viewpoint of TFT advantages, the low-temperature (<600 degrees C) fabrication of TFT circuits is essential to their future progress. The main objective is to realize sufficient electrical characteristics of TFT devices below 600 degrees C, using methods such as MOS interface control, crystalline grain growth, and trap passivation at grain boundaries. This will make it possible to apply TFT circuits not only to much larger substrates but also to concepts such as three-dimensional LSIs.<<ETX>>

Analysis of Degradation Phenomenon Caused by Self-Heating in Low-Temperature-Processed Polycrystalline Silicon Thin Film Transistors

The reliability of low-temperature-processed (425°C) polycrystalline-silicon thin film transistors (poly-Si TFTs) was investigated. For n-channel TFTs, the sub-threshold characteristics shifted in the positive direction when a high voltage stress was applied to them, which is particularly significant in small-size TFTs as well as in wide-channel TFTs. It was verified that the temperature of the TFTs reached over 300°C due to self-heating when this stress was applied. We estimate that the breaking of Si–H bonds and re-generation of dangling bonds in the channel poly-Si layers due to self-heating are responsible for the degradation phenomenon.

Conduction Mechanism of Leakage Current Observed in Metal-Oxide-Semiconductor Transistors and Poly-Si Thin-Film Transistors

It has been confirmed that the leakage current observed in Metal-Oxide-Semiconductor (MOS) transistors and polycrystalline thin-film transistors (poly-Si TFTs) corresponds to activation energies of the current. Two new models of the conduction of leakage current have been proposed on the basis of this correspondence. These models consist of two types of steps: the first step is the thermal emission of an electron occurring in the neighborhood of the drain electrode, and the second step is the tunneling of an electron through a trap state in the band gap. These models have enabled us to explain the conduction mechanism of the leakage current in various devices.

Low Temperature Poly-Si TFTs Using Solid Phase Crystallization of Very Thin Films and an Electron Cyclotron Resonance Chemical Vapor Deposition Gate Insulator

Low temperature (T600°C) polycrystalline silicon thin film transistors (poly-Si TFTs) have been fabricated by solid phase crystallization (SPC) of amorphous silicon (a-Si) films deposited by low pressure chemical vapor deposition (LPCVD). These TFTs are distinguished by the very thin nature of the channel Si layer (25 nm) and the use of an SiO2 gate insulator deposited by electron cyclotron resonance chemical vapor deposition (ECR-CVD). The present process eliminates the need for hydrogenation and produces mobilities greater than 20 cm2/Vs and on/off current ratios greater than 107.

Low temperature CMOS self-aligned poly-Si TFTs and circuit scheme utilizing new ion doping and masking technique

Low-temperature (<or= 600 degrees C) CMOS self-aligned polycrystalline-silicon thin-film transistors have been investigated for liquid crystal displays with integrated drivers fabricated on large glass substrates. In order to achieve a self-aligned structure, a novel non-mass-separated ion doping (1/D) technique featuring a large beam area (over 300 mm square) and high accelerating voltage (maximum: 110 keV) is used for the formation of source and drain regions. In addition, for the application of the novel 1/D technique to CMOS configurations, a novel masking technique is also introduced which makes it simple to fabricate CMOS configurations and eliminates the resist masking process in the ion implantation of impurities. Using these techniques, CMOS circuits such as inverters, ring oscillators, and shift registers were successfully fabricated on glass substrates, and the circuit functionalities were confirmed.<<ETX>>

Analysis of threshold voltage shift caused by bias stress in low temperature poly-Si TFTs

The degradation phenomenon of low temperature (/spl les/425/spl deg/C) polycrystalline-silicon thin film transistors (poly-Si TFTs) caused by self-heating has been investigated. In n-channel TFTs, the subthreshold characteristics are significantly and rapidly shifted in the positive direction. This is particularly marked in wide channel TFTs and/or small size TFTs. In order to improve reliability, TFTs with divided channel patterns have also been introduced.

New degradation phenomenon in wide channel poly-Si TFTs fabricated by low temperature process

A new degradation phenomenon in low temperature (/spl les/425/spl deg/C) polycrystalline-silicon thin film transistors (poly-Si TFTs) has been investigated. The subthreshold characteristics are significantly shifted in the negative direction, which is particularly marked in wide (typical channel width: W=100 /spl mu/m) n-channel TFTs. It is considered that this degradation phenomenon is induced by the generation of holes and increase of the temperature during the operation.

Latest Developments In Liquid Crystal Television Displays

This paper will discuss developments in liquid crystal (LC) television displays, mainly for pocket-size TV sets. There are two types of LC television displays. One is a simple multiplexing type, and the other is an active matrix type. The former type is an easier way to fabricate large and low-cost LC panels than the latter. However, it has serious drawbacks. The contrast gets lower as the duty ratio gets higher. Therefore the TV image of this type inevitably has rather low contrast and resolution. On the other hand, the active matrix type, which consists of active elements in each pixel, has several advantages in overcoming such problems. The metal oxide semiconductor transistors and the amorphous or polycrystalline Si thin-film transistors (TFTs) have possibilities in this application. A full-color LC display, which can be realized by the combina-tion of color filters and poly Si TFT arrays on a transparent substrate, was proven to have excellent color image, close to that of conventional CRTs. Here, several examples of LC television displays, including color, are shown. Some of them are already on the market, and others will be soon.

Transistor and physical properties of polycrystalline silicon films prepared by infralow‐pressure chemical vapor deposition

The infralow‐pressure chemical vapor deposition (ILPCVD) system has been developed to reduce the partial pressure of silane (PSiH4) to the sub‐mTorr order by increasing the pumping speed, while aiming at the improvement of as‐deposited polycrystalline silicon (poly‐Si) film qualities. The films prepared by the system show better physical properties than ordinary low‐pressure chemical vapor deposition (LPCVD) films at fixed temperature (600 °C), so that the low‐temperature processed as‐deposited poly‐Si thin film transistors can be easily and significantly improved, having ON/OFF current ratios of more than 108. Physical analyses have confirmed that the films deposited at temperatures as low as 555 °C by the ILPCVD system are undoubtedly polycrystalline. The fabrication of poly‐Si TFT’s through a low‐temperature process confirms good semiconductive behavior of the films, even when deposited at 555 °C. The superiority of the ILPCVD over other LPCVD’s is explained by the deposition kinetics. The nature of LP...

Polysilicon Thin Film Transistors

PURPOSE:To provide a polysilicon thin-film transistor having a gate electrode of low contact resistance has a compatibility to a process. CONSTITUTION:An operating region 2 consisting of a polysilicon film is formed, a gate insulating film 4 is laminated on source and drain regions 3a and 3b, which come into contact with this region 2, a gate electrode 5 is arranged in such a way as to position over the region 2 via this film 4, the electrode 5 is formed of a lower layer 5a consisting of Ta and an upper layer 5b consisting of a TaMo alloy and a contact resistance between the layer 5b and a connection wiring 9b is made low.