Hitoshi Kuniyasu

Contamination Removal by Single‐Wafer Spin Cleaning with Repetitive Use of Ozonized Water and Dilute HF

We have developed a new technique of single-wafer spin cleaning at room temperature, while alternately supplying ozonized water and dilute HF for only 10 s each onto a rotating silicon wafer through jet nozzles, then repeating the cycle until the surface cleanliness reaches the required level. The new spin cleaning sequence can efficiently remove both particulate and metallic contaminants as well as organic contaminants on the surface of silicon wafers in a short time without increasing the microroughness of the surface. This technique will meet the requirements for stricter wafer cleanliness, larger diameter wafer processing, and greater respect for the environment.

Damage-Free Ultradiluted HF ∕ Nitrogen Jet Spray Cleaning for Particle Removal with Minimal Silicon and Oxide Loss

There has been a trade-off between efficient particle removal and damage minimization to fragile device structures when using mixed-liquid/gas jet spray cleaning of silicon wafers. We have developed an ultradiluted HF/nitrogen jet spray cleaning procedure for single-wafer spin-cleaning, which can efficiently remove particles on both silicon and silicon-dioxide surfaces even at a low nitrogen flow rate without causing damage to fragile 45-nm polysilicon gate structures in a short period. The use of ultradiluted HF can make silicon and oxide loss negligible, below 0.003 nm and 0.03 nm, respectively. This very simple single-step cleaning procedure drastically reduces chemical consumption.

Detection of 30–40-nm Particles on Bulk-Silicon and SOI Wafers Using Deep UV Laser Scattering

As semiconductor devices continue to get smaller, and thus the size of yield-limiting particles decreases, a need has arisen for detecting smaller particles on silicon surfaces. The current minimum detectable diameter of wafer-surface particle-detection systems employing 488-nm wavelength Ar+ gas lasers widely used in semiconductor production lines is, under optimized conditions, 50-60 nm on bulk-silicon surfaces. The sensitivity for SOI wafers, however, is considerably lower than this level due not only to the additional optical reflections from Si/SiO2/Si interfaces within the SOI stack but also to the undesirable light scattering at the rough interfaces. The challenges in meeting the requirement to detect smaller particles specified in the ITRS will be presented. Using a 266-nm solid-state laser, we have developed for semiconductor manufacturing a high sensitivity system capable of detecting particles as small as 30 and 40 nm on unpatterned bulk-silicon wafers and SOI wafers, respectively. Our technique of single-wafer spin cleaning with repetitive use of ozonated water and dilute HF cleaning of silicon wafers can reduce surface microroughness, thus reducing background noise in this system, and providing higher particle-detection sensitivity than conventional RCA cleaning. Defect classification using this system integrated with a review scanning electron microscope will also be discussed

Effect of Wafer Rotation on Photoresist Stripping in Supercritical CO2

Introduction As the demand for higher-speed semiconductor devices increases, interlayer low-k films with smaller dielectric constants are required for higher-speed Cu interconnections at the back end of the line. Such low-k films can be easily damaged by post-dielectric-etch, plasma ashing and post-ash cleaning, raising the effective dielectric constant of the low-k film. Post-ash cleaning is usually carried out using a liquid, such as an aqueous solution and organic solvents. Such liquid phase cleaning usually provides an excellent photoresist stripping effectiveness, while using a liquid for post-ash cleaning results in raising the effective dielectric constant of the low-k film due to the water absorption into the low-k films. An increase in the effective dielectric constant of the interlayer film increases the interconnections’ resistance and capacitance. To alleviate low-k film damage, supercritical carbon dioxide (CO2)-based processing may be used. This technology has been proposed to remove particulate contamination [1] and to remove silicon oxide films in the fabrication of high-aspect-ratio structures [2]. Recently, it has also been shown that supercritical CO2 together with co-solvents can strip the post-dielectric-etch photoresist without plasma ashing from the surface of the low-k film to make Cu/low-k interconnections [3]. Since supercritical fluid has a lower density and viscosity than liquid, the physical force generated on a solid surface by the supercritical fluid flow is smaller than by liquid flow. Hence, it is less effective to strip the photoresist on an entire wafer using supercritical CO2 than using liquid. In order to completely strip the photoresist from a wafer, the physical force generated on a solid surface by the flow of the supercritical fluid must be enhanced. In this study, we have investigated the effect of wafer rotation on the removal of the post-etch photoresist in supercritical CO2.

Effect of Pressure Pulsation on Post-Etch Photoresist Stripping on Low-k Films in Supercritical CO2

As the demand for higher-speed semiconductor devices increases, interlayer low-k films with smaller dielectric constants are required for higher-speed Cu interconnections at the back end of the line. Such low-k films can be easily damaged by post-dielectric-etch, plasma ashing and post-ash cleaning, raising the effective dielectric constant of the low-k film. An increase in the effective dielectric constant of the interlayer film increases the interconnections’ resistance and capacitance.

Chemical Additive Formulations for Particle Removal in SCCO2-Based Cleaning

Introduction As semiconductor device architectures continue to shrink, small feature/high aspect ratio trench and via structures, including cylindrical capacitors and stacked gate electrodes have become common. These structures are formed in close proximity to each other and can become physically bonded together during aqueous cleaning due to the high surface tension of water during the wetting and subsequent drying of the structures. This phenomenon, called stiction, is a common problem in the manufacturing of micro electro mechanical systems (MEMS) devices. Therefore, removal of contamination on these structures without pattern collapse or stiction is difficult. In addition, conventional aqueous chemistries tend to alter the sensitive low-k interlayer dielectric properties during post-etch or post-ash photoresist residue removal because these materials are organic or porous polymer materials. Supercritical carbon dioxide (SCCO2) provides an alternative method for cleaning fragile fine structures or high aspect-ratio structures. SCCO2 diffuses rapidly, has low viscosity, near zero surface tension like a gas, and thus, can penetrate easily into deep trenches and vias. It also enables more effective cleaning without pattern collapse or stictional degradation, in addition to being more cost-effective and having a lower environmental impact compared to wet cleaning techniques. Recently, SCCO2 compositions containing co-solvents have been used to remove post-etch or postash photoresist residues, both organic and inorganic in nature. We have previously reported the successful removal of particles, removal of post-etch residues, and removal of high-dose ionimplant photoresists by the careful choice of chemical additives in SCCO2 formulations [1]. In this paper, we demonstrate the effects of various chemical additives as well as process temperature and pressure in SCCO2/co-solvent solutions on particle removal efficiency (PRE). Correlation of the particle removal efficiency and substrate layer etch rate will be discussed.

Challenges of Finer Particle Detection on Unpatterned Silicon Wafers

As the size of yield‐limiting particles has significantly decreased with the decrease in the feature size of leading‐edge ULSI devices, a clear need has arisen for a system capable of detecting particles of far below 50 nm in diameter on the surface of silicon wafers. If we employ a shorter wavelength (266 nm or below) laser for the laser‐scanning wafer inspection system, its sensitivity level can be raised to the range of 20 to 30 nm in diameter on smooth surfaces. However, so far, silicon surface morphology, such as crystal originated pits (COPs), micro‐scratches, microroughness, as well as residual chemical contamination on the surface of a mirror‐finished wafer, prevents the detector sensitivity from being raised to such a high level. Therefore, before further raising the particle detection sensitivity of the system, we must establish technologies for obtaining a super‐smooth silicon surface by employing scratch‐free precision surface polishing, COP‐free crystal growing/annealing, and microroughness/p...

Challenges of finer particle detection on bulk-silicon and SOI wafers

Introduction As device geometry continues to shrink and die sizes grow, particulate contamination [1, 2] as well as chemical contamination [3, 4] has an ever-increasing impact on device yields. Of the many potential contamination sources, particle generation within processing equipment is by far the most frequent cause of yield loss in the manufacture of modern ULSI devices. In order to enhance the yield, therefore, more stringent particle control is required throughout wafer-processing operations [1, 2]. Fundamental to the reduction of process/equipment-generated contamination is the monitoring of the wafer-surface particle level [5-8]. Automated laser-scanning particle-detection systems have been used in semiconductor manufacturing lines to determine the quantity, size, and location of the particles on unpatterned silicon wafers. As the size of potentially yield-limiting particles has decreased along with the decrease in the feature size of ULSI devices, a clear need has arisen for systems capable of detecting finer particles. In fact, according to the International Technology Roadmap for Semiconductors (ITRS), the requirements for critical particle-size control in semiconductor manufacturing lines will be tightened in accordance with the trend to shrink the feature size of devices, as is shown in Fig. 1 [9]. Although we have started pilot production of 65-nm CMOS devices, the minimum detectable diameter of the currently available wafer-inspection systems remains under optimized conditions at the 50-60-nm level in optical diameter, almost at the same level of the feature size of leading-edge devices. It is obvious that sub-50 nm particle detection is necessary at advanced technology-nodes. At the 65-nm node and beyond, silicon-on-insulator (SOI) wafers will be required for higher performance devices and/or lower power-consumption devices. In the latest edition of ITRS, however, particle detection on SOI wafers was pointed out as one of the metrological challenges brought about by the additional optical reflections from interfaces within the SOI stack [9], as well as even more light-scattering from rough interfaces [10]. In fact, the minimum detectable defect size of the system for inspecting SOI wafers remains in the >> 100 nm range, much larger than the nominal minimum detectable size for bulk-silicon wafers. Finer particle detection on SOI wafers is also a challenge. This paper focuses on particle detection on bulk-silicon and SOI surfaces and describes several challenges faced in providing finer particle detection to meet the ITRS requirements or even surpass them. Emphasis is placed on the importance of the control of silicon surface morphology, such as crystal-originated pits (COPs), micro-scratches, and micro-roughness, which prevent the detection sensitivity from being raised. A new particle-detection system employing a deep-ultraviolet (266 nm) laser as the light source to raise its sensitivity level both on the bulk-silicon and 10 100