Hitoyuki Tagami

Forward error correction based on block turbo code with 3-bit soft decision for 10-Gb/s optical communication systems

The first experimental demonstration of a forward error correction (FEC) for 10-Gb/s optical communication systems based on a block turbo code (BTC) is reported. Key algorithms, e.g., extrinsic information, log-likelihood ratio, and soft decision reliability, are optimized to improve the correction capability. The optimum thresholds for a 3-bit soft decider are investigated analytically. A theoretical prediction is verified by experiment using a novel 3-bit soft decision large scale integrated circuit (LSI) and a BTC encoder/decoder evaluation circuit incorporating a 10-Gb/s return-to-zero on-off keying optical transceiver. A net coding gain of 10.1 dB was achieved with only 24.6% redundancy for an input bit error rate of 1.98/spl times/10/sup -2/. This is only 0.9 dB away from the Shannon limit for a code rate of 0.8 for a binary symmetric channel. Superior tolerance to error bursts given by the adoption of 64-depth interleaving is demonstrated. The ability of the proposed FEC system to achieve a receiver sensitivity of seven photons per information bit when combined with return-to-zero differential phase-shift keying modulation is demonstrated.

Next generation FEC for optical transmission systems

Technical challenges of forward error correction (FEC) are reviewed. Block turbo code having a net coding gain of higher than 10 dB will mature with the development of 3-bit soft decision LSI.

Experimental demonstration of net coding gain of 10.1 dB using 12.4 Gb/s block turbo code with 3-bit soft decision

Turbo FEC for 10 Gb/s optical transmission has been experimentally demonstrated, for the first time. Using a newly developed 3-bit soft decision LSI, a record coding gain was achieved with only 24.6% redundancy for an input BER of 1.98/spl times/10/sup -2/.

10.3-Gb/s Burst-Mode 3R Receiver Incorporating Full AGC Optical Receiver and 82.5-GS/s Over-Sampling CDR for 10G-EPON Systems

In this letter, we developed, for the first time, 10.3-Gb/s burst-mode 3R receiver incorporating a full automatic gain control optical receiver and 82.5-GS/s over-sampling clock and data recovery (CDR) for 10G-EPON. Burst-mode preamplifier, limiting amplifier, and CDR were newly fabricated on 0.13-¿m SiGe bipolar complementary metal-oxide-semiconductor process to completely meet the IEEE802.3av 10G-EPON standards. The 10.3-Gb/s burst-mode 3R receiver successfully achieves the burst receiver sensitivity of -30.1 dBm (at bit error rate (BER) =1 ×10-3) and the dynamic rage more than 24.1 dB (at BER=1 ×10-3) with the assistance of FEC RS(255, 223).

A Burst-Mode Bit-Synchronization IC With Large Tolerance for Pulse-Width Distortion for Gigabit Ethernet PON

A burst-mode bit-synchronization IC applied to the upstream transmission in a gigabit Ethernet passive optical network (PON) was experimentally verified to have a large tolerance for pulse-width distortion within plusmn0.66 UI. The extra tolerance of 0.22 UI over the IEEE 802.3ah specification can be assigned to additional distortion generated at an optical receiver incorporated into an optical line terminal. Such a large tolerance was attained by precisely generated eight-phase clocks based on theoretical analyses of distortion tolerance considering real circuit parameters and by an enhanced data selector incorporating a pulse-width detector to monitor the pulse-widths of isolated bits. The IC developed includes a burst into series transformer to permit connection to commercially available PON LSI developed for serial data transmission in Ethernet systems. The theoretical study into the numbers of allowable bit errors and consecutive pattern matches in byte synchronization established following two conditions: 1) allowable error more than one bit in synchronization pattern with 10-bit length was required to hold the synchronization loss rate to less than a few times per year and 2) consecutive pattern matching more than twice was required to hold the synchronization error rate to less than a few times per year

A 3-bit soft-decision IC for powerful forward error correction in 10-Gb/s optical communication systems

We describe the design concept and performance of a 3-bit soft-decision IC, which opens a vista for new terabit-capacity optical communication systems by dramatically improving the capability of forward error correction (FEC). The proposed soft-decision IC is composed of five functional blocks, i.e., a soft-decider, an error filter, a 3-bit encoder, a 3:48 de-multiplexer, and a clock recovery circuit. The biggest challenge was the soft-decision block regenerating the common data using seven deciders with separate thresholds. We employed a novel SiGe BiCMOS process and a custom BGA package made from low-temperature co-fired ceramics to achieve a high sensitivity of 20 mVpp with a wide phase margin of 270/spl deg/ for 12.4-Gb/s nonreturn-to-zero (NRZ) data signals. The error filter and the 3-bit encoder, which are incorporated in the IC, prevent the degradation of the FEC performance due to signal noise or fluctuations. The 3:48 de-multiplexer provides an accessible interface with the FEC encoder/decoder LSI. The clock recovery circuit, based on a phase-locked-loop technology, fulfilled the jitter tolerance requirements corresponding to ITU-T G.825, even for 55% duty cycle optical return-to-zero (RZ) signals. The 3-bit soft-decision IC, in cooperation with a block turbo encoder/decoder, achieved a record net coding gain of 10.1 dB with 24.6% redundancy, which is only 0.9 dB away from the Shannon limit for a code rate of 0.8 for a binary symmetric channel.

A fully integrated block turbo code FEC for 10 Gb/s optical communication systems

A block turbo code FEC compatible with G.709 has been fully integrated on VLSI. Combining this with a 3-bit soft decision ASIC enabled a net coding gain of 10.1 dB at 12.4 Gb/s with 23.6% redundancy.

32 GS/s Soft Decision LSI in 0.13 µm SiGe BiCMOS for Forward Error Correction in Optical Communications

We have developed a 2-bit 32 GS/s soft decision LSI in 0.13 μm SiGe-BiCMOS. The LSI includes a flash type Analogue-to-Digital converter and an encoder which outputs the soft decision results, which are a hard decision bit and a confidence bit for strong Forward Error Correction. We have confirmed that the LSI has 25 mVpp sensitivity and the LSI enables 2 dB better FEC coding gain than hard decision.

A Simple Method of Jitter Evaluation for Designing Phase-Locked Loops for Optical Communication Systems

A simple method for evaluating jitter generation is proposed for phase-locked loops (PLLs) applied to optical communication systems. The precise but complex expressions in the conventional method involving the phase noise of the voltage-controlled oscillator, the jitter-transfer function of the PLL, and integration using a filter function are greatly simplified with the objective of providing a simple estimate of the jitter generation avoiding iterative design procedures. These simplifications together with the data from the International Telecommunication Union (ITU)-T Recommendations lead to an integral-free expression with only a small number of parameters, which enables jitter evaluation using a hand-held calculator. By applying bandwidth limits to the jitter tolerance and transfer specifications, both the sufficient and insufficient conditions for the phase noise of a voltage-controlled oscillator are obtained to enable the efficient design of a PLL with the jitter generation specified in the ITU-T Recommendations.

Demonstration of 10.3-Gbit/s burst-mode CDR employing 0.13 um SiGe BiCMOS quad-rate sampling IC and data-phase decision-algorithm for 10Gbps-based PON systems

We present a new 10 Gbps-based PON burst-mode CDR with a 0.13 um BiCMOS quad-rate sampling IC and decision-algorithm for optimum recovery-data selection. Instantaneous burst-mode recovery of the first bit with a long 72-bit CID tolerance was successfully achieved.