Ho Kwan Kang

Te doping in the GaAs tunnel junction for GaInP/GaAs tandem solar cells

Heavily tellurium (Te)-doped GaAs layers with diethyltellurium (DETe) grown by metalorganic chemical vapor deposition (MOCVD) were investigated. The existence of Te-rich microprecipitates might degrade both the electrical and optical properties. Compared to Si doping, the tunnel junction diode doped with Te doping revealed lower tunneling resistance. A comparative study using both Si and Te doping in the GaAs tunnel junction of GaInP/GaAs tandem solar cells showed a higher efficiency for Te doping. Therefore, the GaAs tunnel junction with Te doping can be considered to improve the device performance of GaAs-based multi-junction solar cells.

Position-controlled hydrothermal growth of ZnO nanorods on arbitrary substrates with a patterned seed layer via ultraviolet-assisted nanoimprint lithography

A novel technique for the position-controlled growth of ZnO nanorods is established, by combining ultraviolet-assisted nanoimprint lithography (UV-NIL) and hydrothermal growth. Various ZnO nanorod arrays were obtained on silicon substrates, by UV-NIL of ZnO seed patterns with lines of 200 nm wide at a pitch of 1000 nm from a photosensitive ZnO precursor, followed by a position-controlled hydrothermal growth step with varied growth times. It was found that the aspect ratio of ZnO nanorods increased from 2.7 to 11.8 as the growth time was increased from 2 to 6 h. Selected area electron diffraction (SAED) analysis indicates that the root of studied ZnO nanorods consists of both amorphous and polycrystalline phases whereas the stem shows a single-crystalline nature with a preferred (002) growth. ZnO nanorod arrays were also routinely obtained on transparent glass and flexible polyethylene terephthalate (PET). In all cases, ZnO nanorods were observed on both the sidewalls and top surfaces of the ZnO seed patterns with a nanoflower-like structure regardless of substrate substances. This technique offers an alternative method for integrating ZnO nanorods at low temperatures and free of high vacuum, potentially useful in applications such as nanophotonics, photovoltaics and flexible nanoelectronics.

Wafer-scale surface roughening for enhanced light extraction of high power AlGaInP-based light-emitting diodes

A new approach to surface roughening was established and optimized in this paper for enhancing the light extraction of high power AlGaInP-based LEDs, by combining ultraviolet (UV) assisted imprinting with dry etching techniques. In this approach, hexagonal arrays of cone-shaped etch pits are fabricated on the surface of LEDs, forming gradient effective-refractive-index that can mitigate the emission loss due to total internal reflection and therefore increase the light extraction efficiency. For comparison, wafer-scale FLAT-LEDs without any surface roughening, WET-LEDs with surface roughened by wet etching, and DRY-LEDs with surface roughened by varying the dry etching time of the AlGaInP layer, were fabricated and characterized. The average output power for wafer-scale FLAT-LEDs, WET-LEDs, and DRY3-LEDs (optimal) at 350 mA was found to be 102, 140, and 172 mW, respectively, and there was no noticeable electrical degradation with the WET-LEDs and DRY-LEDs. The light output was increased by 37.3% with wet etching, and 68.6% with dry etching surface roughening, respectively, without compromising the electrical performance of LEDs. A total number of 1600 LED chips were tested for each type of LEDs. The yield of chips with an optical output power of 120 mW and above was 0.3% (4 chips), 42.8% (684 chips), and 90.1% (1441 chips) for FLAT-LEDs, WET-LEDs, and DRY3-LEDs, respectively. The dry etching surface roughening approach developed here is potentially useful for the industrial mass production of wafer-scale high power LEDs.

Facile Size-Tunable Fabrication of Functional Tin Dioxide Nanostructures by Multiple Size Reduction Lithography

A novel ultraviolet (UV)-assisted imprinting procedure that employs photosensitive tin(II) 2-ethylhexanoate is presented for the facile size-tunable fabrication of functional tin dioxide (SnO(2)) nanostructures by varying annealing temperatures. These imprinted SnO(2) nanostructures were also used as new masters for size reduction lithography. SnO(2) lines down to 40 nm wide were obtained from a silicon master with 200 nm wide lines by simply performing size reduction lithography twice. This leads to 80 and 87.5% reduction in the width and height of imprinted lines, respectively. An imprinted pattern annealed at 400 °C demonstrated transmittance greater than 90% over the range of 350-700 nm, which is high enough to make the pattern useful as a transparent SnO(2) mold. This demonstrated approach allows the accessibility to size-tunable molds, eliminating the need for conventional expensive imprinting masters with very fine structures, as well as functional SnO(2) nanostructures, potentially useful in applications where ordered surface nanostructures are required, such as photonic crystals, biological sensors, and model catalysts.

Light output enhancement of InGaN/GaN light-emitting diodes with contrasting indium tin-oxide nanopatterned structures

Various nanopatterns on the transparent conducting indium tin oxide (ITO) layer are investigated to enhance the light extraction efficiency of the InGaN/GaN light-emitting diodes (LEDs). Triangular, square, and circular nanohole patterns with the square and hexagonal lattices are fabricated on the ITO layer by an electron beam lithography and inductively coupled plasma dry etching processes. The circular hole pattern with a hexagonal geometry is found to be the most effective among the studied structures. Light output intensity measurements reveal that the circular hole nanopatterned ITO LEDs with a hexagonal lattice show up to 35.6% enhancement of output intensity compared to the sample without nanopatterns.

The Effects of Growth Temperature and Substrate Tilt Angle on GaInP/GaAs Tandem Solar Cells

The performance of GaInP/GaAs tandem solar cells with AlInP growth temperatures of 680 ℃ and 700 ℃ on n-type GaAs (100) substrate with 2° and 6° tilt angles has been investigated. The series resistance and open circuit voltage of the fabricated tandem solar cells are affected by the substrate tilt angles and the growth temperatures of the window layer when zinc is doped in the tunnel diode. With carbon doping as a p-type doping source in the tunnel diode and the effort of current matching between top and bottom cells, GaInP/GaAs tandem solar cell has been exhibited 25.58% efficiency.

Improving GaInP/GaAs/Ge triple junction solar cell efficiency with reduced growth temperature of GaAs base layer

Using GaInP as a nucleation layer, the Ge bottom cell was fabricated with a proper junction depth in the p-n junction and this Ge bottom cell was used to grow GaInP/GaAs/Ge triple junction solar cells. Then, the growth temperature of p-type GaAs base layer in the middle cell was investigated as a means of improving the solar cell efficiency. The solar cell grown at 550°C produced the improved efficiency compared to that grown at 680°C. The result suggests that the growth temperature of GaAs base layer is an important factor to improve the cell efficiency, related to the thermal stability of previously formed bottom cells.

Simple and cost-effective fabrication of size-tunable zinc oxide architectures by multiple size reduction technique

Abstract We present a simple size reduction technique for fabricating 400 nm zinc oxide (ZnO) architectures using a silicon master containing only microscale architectures. In this approach, the overall fabrication, from the master to the molds and the final ZnO architectures, features cost-effective UV photolithography, instead of electron beam lithography or deep-UV photolithography. A photosensitive Zn-containing sol–gel precursor was used to imprint architectures by direct UV-assisted nanoimprint lithography (UV-NIL). The resulting Zn-containing architectures were then converted to ZnO architectures with reduced feature sizes by thermal annealing at 400 °C for 1 h. The imprinted and annealed ZnO architectures were also used as new masters for the size reduction technique. ZnO pillars of 400 nm diameter were obtained from a silicon master with pillars of 1000 nm diameter by simply repeating the size reduction technique. The photosensitivity and contrast of the Zn-containing precursor were measured as 6.5 J cm−2 and 16.5, respectively. Interesting complex ZnO patterns, with both microscale pillars and nanoscale holes, were demonstrated by the combination of dose-controlled UV exposure and a two-step UV-NIL.

Numerical Simulation of GaInP/AlInP Window Layer For High Concentration Photovoltaic Cells

The feasibility of the GaInP/AlInP window layer, proposed to prevent an unintentional thin‐film degrading the performance of anti‐reflection coating, on a multi‐junction photovoltaic cell was investigated by using two dimensional numerical simulation. Simulated and calibrated GaInP/GaAs/InGaAs triple‐junction solar cell under AM 1.5 global illumination showed exactly the same open circuit voltage, and 0.4% efficiency discrepancy compared with measured data. Based on the simulation results, a 5 nm‐thick GaInP‐oxidation stop layer with a 25 nm‐thick AlInP window layer on the GaInP/GaAs/InGaAs triple‐junction solar cell provided both 0.35%‐efficiency and 30%‐concentration ratio increment.

Internal stress-assisted epitaxial lift-off process for flexible thin film (In)GaAs solar cells on metal foil

Flexible thin film (In)GaAs solar cells are grown by metalorganic chemical vapor deposition on GaAs substrates and transferred to 30 μm thick Au foil by internal stress-assisted epitaxial lift-off processes. The internal stress is induced by replacing the solar cell epi-layers from GaAs to In0.015Ga0.985As, which has a slightly larger lattice constant. The compressive strained layer thickness was varied from 0 to 4.5 μm to investigate the influence of the internal stress on the epitaxial lift-off time. The etching time in the epitaxial lift-off process was reduced from 36 to 4 h by employing a GaAs/In0.015Ga0.985As heterojunction structure that has a compressive film stress of −59.0 MPa. We found that the partially strained epi-structure contributed to the much faster lateral etching rate with spontaneous bending. Although an efficiency degradation problem occurred in the strained solar cell, it was solved by optimizing the epitaxial growth conditions.