Hoi Lee

A Transient-Enhanced Low-Quiescent Current Low-Dropout Regulator With Buffer Impedance Attenuation

This paper presents a low-dropout regulator (LDO) for portable applications with an impedance-attenuated buffer for driving the pass device. Dynamically-biased shunt feedback is proposed in the buffer to lower its output resistance such that the pole at the gate of the pass device is pushed to high frequencies without dissipating large quiescent current. By employing the current-buffer compensation, only a single pole is realized within the regulation loop unity-gain bandwidth and over 65deg phase margin is achieved under the full range of the load current in the LDO. The LDO thus achieves stability without using any low-frequency zero. The maximum output-voltage variation can be minimized during load transients even if a small output capacitor is used. The LDO with the proposed impedance-attenuated buffer has been implemented in a 0.35-mum twin-well CMOS process. The proposed LDO dissipates 20-muA quiescent current at no-load condition and is able to deliver up to 200-mA load current. With a 1-muF output capacitor, the maximum transient output-voltage variation is within 3% of the output voltage with load step changes of 200 mA/100 ns.

Active-feedback frequency-compensation technique for low-power multistage amplifiers

An active-feedback frequency-compensation (AFFC) technique for low-power operational amplifiers is presented in this paper. With an active-feedback mechanism, a high-speed block separates the low-frequency high-gain path and high-frequency signal path such that high gain and wide bandwidth can be achieved simultaneously in the AFFC amplifier. The gain stage in the active-feedback network also reduces the size of the compensation capacitors such that the overall chip area of the amplifier becomes smaller and the slew rate is improved. Furthermore, the presence of a left-half-plane zero in the proposed AFFC topology improves the stability and settling behavior of the amplifier. Three-stage amplifiers based on AFFC and nested-Miller compensation (NMC) techniques have been implemented by a commercial 0.8-/spl mu/m CMOS process. When driving a 120-pF capacitive load, the AFFC amplifier achieves over 100-dB dc gain, 4.5-MHz gain-bandwidth product (GBW) , 65/spl deg/ phase margin, and 1.5-V//spl mu/s average slew rate, while only dissipating 400-/spl mu/W power at a 2-V supply. Compared to a three-stage NMC amplifier, the proposed AFFC amplifier provides improvement in both the GBW and slew rate by 11 times and reduces the chip area by 2.3 times without significant increase in the power consumption.

An Efficiency-Enhanced CMOS Rectifier With Unbalanced-Biased Comparators for Transcutaneous-Powered High-Current Implants

This paper presents an efficiency-enhanced integrated full-wave CMOS rectifier for the transcutaneous power transmission in high-current biomedical implants. The comparator-controlled switches are developed to minimize the voltage drop along the conducting path while achieving the unidirectional current flow. The proposed unbalanced-biasing scheme also minimizes the reverse leakage current of the rectifier under different input amplitudes, thereby optimizing the rectifier power efficiency. Moreover, the proposed rectifier is able to self start and operates at low input amplitudes. Implemented in a standard 0.35 mum CMOS process with maximum threshold voltages of |Vthp| = 0.82 V and Vthn = 0.69 V, the rectifier can source a maximum output current of 20 mA and operate properly with inputs of different amplitudes and frequencies. With a 1.5 MHz input of 1.2 V amplitude, the proposed rectifier can achieve the peak voltage conversion ratio of 95% and the power efficiency of at least 82%.

Design of low-power analog drivers based on slew-rate enhancement circuits for CMOS low-dropout regulators

Low-power analog driver based on a single-stage amplifier with an embedded current-detection slew-rate enhancement (SRE) circuit is presented. By developing a systematic way to design both the response time and optimal sizing of driving transistors in the SRE circuit, the SRE circuit can be controlled to turn on or turn off properly. In addition, the analog driver only dissipates low static power and its transient responses are significantly improved without transient overshoot when driving large capacitive loads. Implemented in a 0.6-/spl mu/m CMOS process, a current-mirror amplifier with the current-detection SRE circuit has achieved over 43 times improvement in both slew rate and 1% settling time when driving a 470-pF load capacitor. When the proposed analog driver is employed in a 50-mA CMOS low-dropout regulator (LDO), the resultant load transient response of the LDO has 2-fold improvement for the maximum load-current change, while the total quiescent current is only increased by less than 3%.

A dual-path bandwidth extension amplifier topology with dual-loop parallel compensation

A dual-path amplifier topology with dual-loop parallel compensation technique is proposed for low-power three-stage amplifiers. By using two parallel high-speed paths for high-frequency signal propagation, there is no passive capacitive feedback network loaded at the amplifier output. Both the bandwidth and slew rate are thus significantly improved. Implemented in a 0.6-/spl mu/m CMOS process, the proposed three-stage amplifier has over 100-dB gain, 7-MHz gain-bandwidth product, and 3.3-V//spl mu/s average slew rate while only dissipating 330 /spl mu/W at 1.5 V, when driving a 25-k/spl Omega///120-pF load. The proposed amplifier achieves at least two times improvement in bandwidth-to-power and slew-rate-to-power efficiencies than all other reported multistage amplifiers using different compensation topologies.

Advances in active-feedback frequency compensation with power optimization and transient improvement

This paper presents a low-power stability strategy to significantly reduce the power consumption of a three-stage amplifier using active-feedback frequency compensation (AFFC). The bandwidth of the amplifier can also be enhanced. Simulation results verify that the power dissipation of the AFFC amplifier is reduced by 43% and the bandwidth is improved by 32.5% by using the proposed stability strategy. In addition, a dynamic feedforward stage (DFS), which can be embedded into the AFFC amplifier to improve the transient responses without consuming extra power, is proposed. Implemented in a 0.6-/spl mu/m CMOS process, experimental results show that both AFFC amplifiers with and without DFS achieve almost the same small-signal performances while the amplifier with DFS improves both the negative slew rate and negative 1% settling time by two times.

Switching noise and shoot-through current reduction techniques for switched-capacitor voltage doubler

Switching noise and shoot-through current reduction techniques for switched-capacitor voltage doublers based on cross-coupled structure are presented. The intuitive analysis of the shoot-through current and switching noise generation processes in the doubler is first reported. Break-before-make mechanism is adopted to minimize the shoot-through current, thereby greatly reducing the no-load supply current dissipation and improving the light-load power efficiency of the voltage doubler. In addition, by employing gate-slope reduction technique at the serial power transistor during turn-on, the switching noise of the voltage doubler is significantly lowered. Two voltage doublers with and without the proposed circuit techniques have been fabricated in a 0.6-/spl mu/m CMOS process. Experimental results verify that the total supply current at no-load condition of the proposed voltage doubler is reduced by two fold and its switching noise is decreased by 2.5 times.

A 5-MHz 91% Peak-Power-Efficiency Buck Regulator With Auto-Selectable Peak- and Valley-Current Control

This paper presents a multi-MHz buck regulator for portable applications using an auto-selectable peak- and valley-current control (ASPVCC) scheme. The proposed ASPVCC scheme can enable the current-mode buck regulator to reduce the settling-time requirement of the current sensing by two times. In addition, the dynamically biased shunt feedback technique is employed to improve the sensing speed and the sensing accuracy of both the peak and valley current sensors. With both ASPVCC scheme and advanced current sensors, the buck regulator can thus operate at high switching frequencies with a wide range of duty ratios for reducing the required off-chip inductance. The proposed current-mode buck regulator was fabricated in a standard 0.35-μm CMOS process and occupies a small chip area of 0.54 mm2. Measurement results show that the buck regulator can deliver a maximum output current of 500 mA, operate at 5 MHz with a wide duty-ratio range of about 0.6, use a small-value off-chip inductor of 1 μH, and achieve the peak power efficiency of 91%.

An Integrated Speed- and Accuracy-Enhanced CMOS Current Sensor With Dynamically Biased Shunt Feedback for Current-Mode Buck Regulators

This paper presents a new compact on-chip current-sensing circuit to enable current-mode buck regulators operating at a high switching frequency for reducing the inductor profile. A dynamically biased shunt feedback technique is developed in the proposed current sensor to push nondominant poles to higher frequencies, thereby improving the speed and stability of the current sensor under a wide range of load currents. A feedforward gain stage in the proposed current sensor also increases the dc loop-gain magnitude and thus enhances the accuracy of the current sensing. A current-mode buck regulator with the proposed current sensor has been implemented in a standard 0.35-μm CMOS process. Measurement results show that the proposed current sensor can achieve 95% sensing accuracy and <;; 50-ns settling time. The buck converter can thus operate properly at the switching frequency of 2.5 MHz with the duty cycle down to 0.3. The output ripple voltage of the regulator is <;; 43 mV with a 4.7-μF off-chip capacitor and a 2.2-μH off-chip inductor. The power efficiency of the buck regulator achieves above 80% over the load current ranging from 25 to 500 mA.

Dual Active-Capacitive-Feedback Compensation for Low-Power Large-Capacitive-Load Three-Stage Amplifiers

A dual active-capacitive-feedback compensation (DACFC) scheme for low-power three-stage amplifiers with large capacitive loads is presented in this paper. Dual high-speed active-capacitive-feedback paths enable the non-dominant complex poles of the amplifier to be located at high frequencies for bandwidth extension under low-power condition. The proposed DACFC amplifier also consists of two left-half-plane (LHP) zeros that relax the stability criteria for further improving the gain-bandwidth product (GBW) and reducing the required compensation capacitance of the amplifier. Moreover, the transient response of the DACFC amplifier is enhanced via the use of the small compensation capacitance and the presence of push-pull second and output stages. Two three-stage amplifiers using the proposed DACFC and the well-known nested Miller compensation (NMC) have been implemented in a standard 0.35-μm CMOS process. The proposed DACFC amplifier uses a total compensation capacitance of 2.2 pF and is robust in stability with a phase margin of >;58° under the variation of the load capacitance between 300 pF and 800 pF. When driving a 500-pF//25-kΩ load, the DACFC three-stage amplifier improves the GBW-to-power by 66 times, enhances the slew rate-to-power by 51 times, and reduces the chip area by 33 times, as compared to the conventional NMC counterpart.