Holger Bartolf

Study of 4H-SiC Schottky Diode Designs for 3.3kV Applications

The static performance of different active and termination area designs for SiC-based Schottky diodes, suitable for 3.3kV applications, were investigated by means of extensive numerical simulations. We found quantitatively that the high electric field of SiC close to avalanche-breakdown is shielded most effectively from the Schottky interface by a trench-based design. Moreover, we conclude that the edge termination design with junction termination extension and four implanted p+ guard rings is most robust against oxide interfacial charge.

Two-Dimensional Carrier Profiling on Lightly Doped n-Type 4H-SiC Epitaxially Grown Layers

Electronically active dopant profiles of epitaxially grown n-type 4H-SiC calibration layer structures with concentrations ranging from 3.1015 cm-3 to 1·1019 cm-3 have been investigated by non-contact Scanning Probe Microscopy (SPM) methods. We have shown that Kelvin Probe Force Microscopy (KPFM) and Electrostatic Force Microscopy (EFM) are capable of resolving two-dimensional carrier maps in the low doping concentration regime with nanoscale spatial resolution. Furthermore, different information depths of this wide band gap semiconductor material could be assessed due to the inherent properties of each profiling method. We additionally observed a resolution enhancement under laser illumination which we explain by reduced band-bending conditions. To gauge our SPM signals, we utilized epitaxially grown layers which were calibrated, in terms of dopant concentration, by C-V measurements.

Optimization of 1700V 4H-SiC JBS Diode Parameters

The in-depth design optimization of the active layer of the 1700V class 4H-SiC JBS/MPS diode structure is discussed. The important design parameters such as junction depth (d), width (w) of p+ areas, and spacing (s) between them were optimized for the best possible trade-off between the unipolar ON-state voltage drop, the OFF-state breakdown voltage, and the bipolar surge current capability. The optimization was performed using a state-of-the-art simulator using device models calibrated on a commercially available JBS rectifier. The results show that the spacing s between the p+ regions is the most decisive parameter which has to be properly designed according to the required voltage class. For the 1700 V voltage class, s should be between 2 to 4 μm and the s/w ratio should be kept low. The depth d of the p+ pattern has a pronounced impact on the ignition of bipolar action such that with decreasing d the surge current capability decreases significantly.

Passivation of 4H-SiC/SiO2 Interface Traps by Oxidation of a Thin Silicon Nitride Layer

The effect of the alternative nitridation process of the 4H-SiC/SiO2 interface by introduction of a thin silicon nitride layer on the electrical properties of the gate oxide has been investigated. C-V and G-V measurements on inversion-channel MOS devices revealed similar results to the conventional N2O oxidation. Higher field-effect mobility values are achieved due to lower interface roughness of the alternative nitridation process. However, insignificant degradation of the reliability was observed.

Inversion-Channel MOS Devices for Characterization of 4H-SiC/SiO2 Interfaces

Electrical properties of the gate oxides thermally grown in N2O on n-type and p-type 4H-SiC have been compared using conventional MOS structure and inversion-channel MOS structure, respectively. Sufficient difference in the electrical properties of the gate oxides grown on n-type and p-type 4H-SiC was revealed. We conclude that the gate oxide process optimisation using inversion-channel MOS devices is superior as compared to the conventional MOS structure.

On the influence of active area design on the performance of SiC JBS diodes

This paper presents an investigation regarding the influence of the active area design on the static and dynamic performance of SiC JBS diodes. The analysis has been performed on fabricated JBS diodes, rated for 1.7kV applications. For the active area layout, both stripe and hexagonal cell patterns have been used for the implanted p+ regions.

Junction Barrier Schottky (JBS) Rectifier Interface Engineering Facilitated by Two-Dimensional (2D) Dopant Imaging

The shielding cell architecture of a buried grid (BG) Junction Barrier Schottky (JBS) diode consisting of multiple consecutive p+-implanted stripes below the metal/semiconductor interface has been observed by performing non-contact Scanning Probe Microscopy (SPM) and Secondary Electron Potential Contrast (SEPC) measurements on the cross-section of the device. We have demonstrated that these techniques succeeded in mapping the two-dimensional carrier distribution inside the active area of the device, however with different resolution and quantification possibilities.

High Channel Mobility 4H-SiC MOSFETs by As and P Implantation Prior to Thermal Oxidation in N2O Atmosphere

High channel mobility 4H-SiC MOSFETs have been demonstrated by phosphorus and arsenic implantation prior to thermal oxidation in N2O. The maximum field-effect mobility of 81 and 114 cm2/Vs were achieved, respectively. The MOSFET fabrication was done on lightly aluminium doped p-type epitaxial layers and on heavily aluminium implanted p-well.

Development of power semiconductors by quantitative nanoscale dopant imaging

Dopant imaging at high spatial resolution provides an indispensable tool for the improvement of novel power semiconductor devices. Cross-sections of next-generation devices based on Silicon (Si) and Silicon Carbide (SiC) have been investigated by scanning probe microscopy (SPM) derived dopant imaging techniques in a dedicated ultra-high vacuum (UHV) setup to determine the active carrier concentration in differently doped areas of the device under investigation. The physical location of the metallurgical p/n-junction and the associated space-charge regions (SCR) can be experimentally characterized with nanoscale precision. Furthermore, fabrication processes benefit from a reduced number of manufacturing cycles due to the profound knowledge on the evolution of dopant atoms and their corresponding impact on the device performance. Typical power device doping-levels in the range of 1014 cm-3 to 1014 cm-3 can be sensed by the here discussed approach.

Comparison of the Planar-JBS against the Trench-MOS Rectifier-Design Based on 4H-SiC for 3.3 kV Applications

We compare the static electronic performance of the state-of-the-art Junction-Barrier-Schottky (JBS) rectifier (manufactured by ion-implantation) against the Trench-MOS Barrier Schottky (TMBS) rectifier (manufactured by trench-etching and subsequent oxidation). In our 2D numerical simulations, we have chosen identical specifications for the epitaxial drift-layer (3.3 kV application voltage, e.g. traction) and back-side device-design, while investigating the impact of the top-cell active area design on both rectifier IV-characteristics. To enable a meaningful comparison, we designed the depth d of the shields for the electric field E equally deep (p+ peak-plateau dJBS equals trench-depth dt), such that the peak E-field (close to avalanche breakdown) inside the drift-layer of the device is located at a comparable depth near the anode-side of the rectifier (see Fig. 2). By studying systematically the ratio between shield-to Schottky contact-length (w/s ratio), we found that the unipolar conduction state of the TMBS design is basically unaffected by enlarging the Schottky-contact length s, which is enterly different for the JBS-case.