Holger Wenske

A 14b 40MS/s Redundant SAR ADC with 480MHz Clock in 0.13pm CMOS

A 2-channel time-interleaved 40MS/s SAR ADC with redundancy is presented. The 0.13mum 1.5V CMOS design runs at 480MHz iteration clock and features 89dB THD and 81dB SNDR. Including the PLL, the second-order anti-alias filter, and reference buffer, the chip consumes 66mW and occupies 0.55mm2.

A 285 mW CMOS single chip analog front end for G.SHDSL

The Single-Pair High-Speed Digital Subscriber Line (G.SHDSL) standard defines full duplex transmission on a single copper loop with variable data rates between 192kb/s and 2.3Mb/s. The achievable loop length varies between 6.3kft and 19.81kft (American Standard), depending on the selected data rate. G.SHDSL uses a trellis-coded PAM-modulation scheme with echo compensation for bandwidth-efficient data transmission in the baseband. A flat symmetrical spectral power density up to 384kHz with a transmit power of 13.5dBm (14.5dBm in Europe above 2.048Mb/s) guarantees spectral compatibility with existing xDSL services. The system concept presented here, together with 3.2 peak-to-rms ratio of the transmit signal, provide the basis for a low power single-chip implementation of the analog front end.