Hong-Hee Lee

Designing Impedance Network at Quasi Z-Source Inverters by Considering ESR in the Capacitor

This paper proposes the method to design the parameters of an impedance network at three-phase QZSI(quasi Z-source inverter) by considering an equivalent series resistance (ESR) in the capacitor. The equations of both two capacitor voltages and two inductor currents are derived at three operating modes of the QZSI. The capacitor voltage ripples caused by the ESR in the capacitor at the transition state of operating modes are calculated. Based on the ripples of both the capacitor voltages and inductor currents, the optimal values of capacitor and inductor are designed. The simulation studies using PSIM and experimental results with DSP are carried out to verify the performance of design method.

A study on controller design for network induced time delay system

In the NCS (networked control systems) whose control loops are closed through the serial communication channel, some important issues are network-induced time delay, multiple-packet transmission and data packet dropouts, which are caused by MAC (Medium Access Control) protocol and/or scheduling algorithm, packet size constraint of applied network and fault of the communication channel, respectively. Among these issues, the most important problem which should be overcome from the point of controller design in NCS is the network-induced time delay because the multiplepacket transmission and the data packet dropout problems can be solved by proper assumptions. As is well known, the network-induced time delay can be constant, time-varying, or random variable depending on protocol and/or scheduling algorithm, but it is needed to compensate any kinds of time delay by a proper controller. This paper focuses on LMI(Linear Matrix Inequality) based output feedback controller design in order to compensate network-induced time delay which is the limited time-varying delay in NCS. In our study, the effect of time-varying delay is regarded as a variable in a discrete-time model of NCS within sampling period. The effectiveness of the proposed output feedback controller is shown to be useful by example.

Robust induction motor control on network-based control systems

In network-based distributed control systems, it is important to compensate the problem due to the transport delay especially in multi-motor driving systems. This paper deals with the robust controller design of the induction motor control scheme which can be applicable to time delay systems such as network-based control systems. The approach taken in this paper assumes that the induction motors are driven with a field orientation control algorithm through the control network. In this paper, to overcome the performance degradation due to transport delay, we have used a memoryless controller. Simulation results are given to prove the control performance.

Synchronization Techniques for Single-Phase and Three-Phase Grid Connected Inverters using PLL Algorithm

A PLL system has widely used for synchronizing the grid voltage at the grid-connected inverter for supplying power from the PV generation systems. In this paper, a PLL algorithm without both the loop filter and PI controller is suggested for improving the performance of synchronization at the single-phase and three-phase grid connected inverters. In order that the output voltage of a phase detector in the PLL has only a dc voltage, and it approaches to 0 when the synchronization signal is locked to the grid voltage, the feedback signals are determined by using two-phase voltages. After the PLL system with a proportional controller is modelled with the small signal analysis, the stability and steady-state error are investigated. Through the simulation studies and experimental results, the performances of the proposed PLL algorithm are verified.

Implementation of an FPGA-based Multi-Carrier PWM Techniques for Multilevel Inverter

Multi-level inverters have drawn much of attention in recent years because it can meet the demand of high power applications and good power quality associated with reduced harmonic distortion. As the number of voltage level increases, field programmable gate arrays (FPGAs) are suitable for the implementation of multi-level modulation algorithm. This paper proposes the implementation method for generating PWM pulses at the three phase diode clamped five-level inverter using FPGA. The strategy for communicating stably the data of three-phase reference voltages between the DSP and FPGA is suggested. The techniques for generating PWM signals based on a multi-carrier modulation method are carried out through the experiments with 32-bit DSP and Cyclone-III FPGA.