Hong Luo

Temperature-aware NBTI modeling and the impact of input vector control on performance degradation

As technology scales, negative bias temperature instability (NBTI), which causes temporal performance degradation in digital circuits by affecting PMOS threshold voltage, is emerging as one of the major circuit reliability concerns. In this paper, the authors first investigate the impact of NBTI on PMOS devices and propose a novel temporal performance degradation model for digital circuits considering the temperature difference between active and standby mode. For the first time, the impact of input vector control (to minimize standby leakage) on the NBTI is investigated. Minimum leakage vectors, which lead to minimum circuit performance degradation and remains maximum leakage reduction rate, are selected and used during the standby mode. Furthermore, the potential to save the circuit performance degradation by internal node control techniques during circuit standby mode is discussed. Our simulation results show that: 1) the active and standby time ratio and the standby mode temperature have considerable impact on the circuit performance degradation; 2) the NBTI-aware IVC technique leads to an average 3% savings of the total circuit degradation; while the potential of internal node control may lead to 10% savings of the total circuit degradation

ESE: Efficient Speech Recognition Engine with Sparse LSTM on FPGA

Long Short-Term Memory (LSTM) is widely used in speech recognition. In order to achieve higher prediction accuracy, machine learning scientists have built increasingly larger models. Such large model is both computation intensive and memory intensive. Deploying such bulky model results in high power consumption and leads to a high total cost of ownership (TCO) of a data center. To speedup the prediction and make it energy efficient, we first propose a load-balance-aware pruning method that can compress the LSTM model size by 20x (10x from pruning and 2x from quantization) with negligible loss of the prediction accuracy. The pruned model is friendly for parallel processing. Next, we propose a scheduler that encodes and partitions the compressed model to multiple PEs for parallelism and schedule the complicated LSTM data flow. Finally, we design the hardware architecture, named Efficient Speech Recognition Engine (ESE) that works directly on the sparse LSTM model. Implemented on Xilinx KU060 FPGA running at 200MHz, ESE has a performance of 282 GOPS working directly on the sparse LSTM network, corresponding to 2.52 TOPS on the dense one, and processes a full LSTM for speech recognition with a power dissipation of 41 Watts. Evaluated on the LSTM for speech recognition benchmark, ESE is 43x and 3x faster than Core i7 5930k CPU and Pascal Titan X GPU implementations. It achieves 40x and 11.5x higher energy efficiency compared with the CPU and GPU respectively.

Temperature-Aware NBTI Modeling and the Impact of Standby Leakage Reduction Techniques on Circuit Performance Degradation

As technology scales, Negative Bias Temperature Instability (NBTI), which causes temporal performance degradation in digital circuits by affecting PMOS threshold voltage, is emerging as one of the major circuit reliability concerns. In this paper, we first investigate the impact of NBTI on PMOS devices and propose a temporal performance degradation model that considers the temperature variation between active and standby mode. We then discuss the resemblance between NBTI and leakage mechanisms, and find out that the impact of input vector and internal node on leakage and NBTI is different; hence, leakage and NBTI should be optimized simultaneously. Based on this, we study the impact of standby leakage reduction techniques (including input vector control and sleep transistor insertion) on circuit performance degradation considering active and standby temperature differences. We demonstrate the potential mitigation of the circuit performance degradation by these techniques.

New-age: a negative bias temperature instability-estimation framework for microarchitectural components

Degradation of device parameters over the lifetime of a system is emerging as a significant threat to system reliability. Among the aging mechanisms, wearout resulting from Negative Bias Temperature Instability (NBTI) is of particular concern in deep submicron technology generations. While there has been significant effort at the device and circuit level to model and characterize the impact of NBTI, the analysis of NBTI’s impact at the architectural level is still at its infancy. To facilitate architectural level aging analysis, a tool capable of evaluating NBTI vulnerabilities early in the design cycle has been developed that evaluates timing degradation due to NBTI. The tool includes workload-based temperature and performance degradation analysis across a variety of technologies and operating conditions, revealing a complex interplay between factors influencing NBTI timing degradation.

A framework for estimating NBTI degradation of microarchitectural components

Degradation of device parameters over the lifetime of a system is emerging as a significant threat to system reliability. Among the aging mechanisms, wearout resulting from NBTI is of particular concern in deep submicron technology generations. To facilitate architectural level aging analysis, a tool capable of evaluating NBTI vulnerabilities early in the design cycle has been developed. The tool includes workload-based temperature and performance degradation analysis across a variety of technologies and operating conditions, revealing a complex interplay between factors influencing NBTI timing degradation.

Circuit-level delay modeling considering both TDDB and NBTI

With aggressive scaling down of the technology node, the time-dependent dielectric breakdown (TDDB) and negative biased temperature instability (NBTI) are becoming key challenges for circuit designers. Both TDDB and NBTI significantly degrade the electrical characteristic of the CMOS devices. A delay model considering TDDB and NBTI is proposed in this paper. The output degradation of the breakdown gate is considered in circuit-level delay analysis. Traditionally, it is considered the TDDB degradation always degrades the circuit delay. However, this paper shows the TDDB effect may boost up the circuit speed. The spatial correlation of TDDB effect is also demonstrated in this paper and shows the difference of 40% in circuit delay depending on the location of the breakdown gate in the signal path.

Application specific sensor node architecture optimization—Experiences from field deployments

The Mote architecture is the most popular platform used in wireless sensor network applications. In this architecture, microcontroller is responsible for all jobs, such as scheduling, sampling, computing, and communication. In the past one year, two practical applications: bridge structural health monitoring system and rare animal monitoring system are developed and deployed in Wuxi and Beijing, China. It is found that Mote architecture faces many problems in these applications. First, sampling, computing, and communication conflicts with each other if they are not carefully scheduled; second, some jobs are very difficult even impossible to be implemented in the microcontroller; third, low power, one of the most fundamental design principles in wireless sensor networks, is sometimes violated with all jobs implemented in the microcontroller. Software optimization is attempted to solve these problems. However, the effect is very limited. Application specific sensor node architecture is necessary for implementing these applications efficiently. In this paper, we propose new application specific sensor node architecture and corresponding design principles and then applied them in the field deployments. Experimental and field tests show that these architectures are more efficient than Mote architecture in these applications.

The impact of correlation between NBTI and TDDB on the performance of digital circuits

With integrated circuits scale into the nano-scale era, aging effect becomes one of the most important design challenges. Both the biased temperature instability (BTI) and time-dependent dielectric breakdown (TDDB) can significantly degrade the performance of the circuits. In this paper, we consider the correlation between BTI and TDDB, and apply the correlation model to digital circuit analysis for the first time. The results show that the correlation can lead to 10.42% further more delay degradation.

Accurate and Fast Estimation of Junction Band-to-Band Leakage in Nanometer-Scale MOSFET

The estimation and optimization of leakage power become more and more important with technology scalling. Besides subthreshold and gate leakage, the band-to-band (BTBT) junction leakage plays a significant role in total leakage and thus accurate estimation is one of the most important missions in circuit simulation. Today, the current leakage estimating models are still not accurate enough or slow. Shiue et al. (2001) had developed some methods based on extremely empirical models, but these models can not estimate the effect of process variations. On the other side, Kurimoto et al. (1989) had constructed lots of device models to estimate BTBT current, but due to the performance problems, these models could not be applied for circuit simulation directly. In this paper, we propose an accurate and fast model for estimating BTBT leakage, and this model could obtain a result consistent with the simulation result of MEDICI, while the speed of our model is 300X faster. Moreover, this model is physical-based. Hence it is suitable for leakage analysis for large-scale circuits and the effect of process variations can be estimated

An instruction-level analytical power model for designing the low power systems on a chip

In this paper, an instruction-level analytical power model for the low power systems on a chip (SoC) is proposed. The inter-instruction effects are obtained with combining different instructions for program running in a processor, such as DSP, CPU for embedded SoC. Variations in base costs as different operands and addresses are also observed. Finally, power consumption of one section of DSP program is measured and compared with the estimated value by our model, which shows that the proposed model is simple and effective for estimating the power consumption of program and it is useful for further software/hardware co-design of SoC