Hongchao Zheng

FITVS: A FPGA-Based Emulation Tool For High-Efficiency Hardness Evaluation

This paper presents an improved tool called FITVS (Fault Injection Tool for Validating SEE) using the FPGA-based emulation system for fault grading. A novel library-replace-modeling technique that can quickly and easily perform SEE by injecting faults into the circuit nodes is proposed. It helps IC designers to enhance the quality of their design by providing the sensitivity information of all nodes. Also the fault injection effectiveness is improved with relative to the traditional methods by utilizing C# program and FPGA emulation, and the speed of injection can reach the order of lus/fault.

The single-event effect evaluation technology for nano integrated circuits

Single-event effects of nano scale integrated circuits are investigated. Evaluation methods for single-event transients, single-event upsets, and single-event functional interrupts in nano circuits are summarized and classified in detail. The difficulties in SEE testing are discussed as well as the development direction of test technology, with emphasis placed on the experimental evaluation of a nano circuit under heavy ion, proton, and laser irradiation. The conclusions in this paper are based on many years of testing at accelerator facilities and our present understanding of the mechanisms for SEEs, which have been well verified experimentally.

A Monte Carlo-based control signal generator for single event effetc (SEE) fault injection

In this paper a single event effect (SEE) fault injection control signal generator based on Monte Carlo method is proposed. Fault control signal generated by the traditional SEE fault injection emulation method for VLSI does not take the speciality of the space environment and the electrical characteristics of the circuit into account. Whereas the signal generator presented in this paper takes advantage of the Monte Carlo method to perform curve fitting on the space particle sample data, as well as to evaluate the circuit node capacitance characteristics and the deposit energy of multiple incidence angles, thereby overcomes the two aspects of disadvantages mentioned before and makes the fault injection emulation approach closer to the real SEE. At the same time C# program and FPGA hardware accelerated emulation are introduced to improve the speed and efficiency of the fault injection control signal generation which makes the proposed generator suitable for generating fault control signal of SEE fault injection emulation.

Experiment and analysis of transient ionizing radiation effects in 0.5um bulk CMOS buffer

A Testing system for transient irradiation experiment is designed to explore the transient ionizing radiation effects in an 8bit three state output bidirectional buffer. Signal responses of this circuit irradiated with high dose rate gamma rays are obtained. In particular, changes of output and supply voltage for the circuit are focused. The experiment results show that the recovery situation of signal depends on the disturbance-rejecting capability of supply voltage.

High energy proton and heavy ion induced single event transient in 65-nm CMOS technology

As technology extends to nanometer scales, the critical charge to induce a single event decreases along with the technology node, and the threshold linear energy transfer (LET) for a soft error also decreases [1]. Meanwhile, as the operating frequency of the integrated circuit (IC) increases, the possibility for single event transients (SETs) to be captured increases. Moreover, SETs have exceeded single event upsets (SEUs) and become the dominant source of soft errors in space-used integrated circuits [2]. The distribution of SET pulse widths is the critical basis for SET mitigation [3]. Placing temporal filters at inputs of storage elements is a common way to achieve SET hardening. When the pulse width is smaller than the filter’s delay, the filter output is a floating value and retains at the previous value. However, the temporal redundancy fails for long SETs. To efficiently mitigate SETs by design, it is essential to know the pulse widths of the SETs using a specific technology and explore those factors that influence the SET pulse widths. Experiment details. A pulse width test chip is designed and fabricated with a 65-nm bulk-Si 1P7M CMOS process. The target part contains target chains of many typical logic cells where the SETs are generated under irradiation. The target chain consisting of inverters, nand gates and nor gates, named INV, NAND and NOR, respectively. To reduce the SET propagation-induced pulse broadening (PIPB), the target structure is designed as a parallel one [4]. The pulse capture part determines the temporal width of the generated SETs and the pulse capture circuit has a wide measurement range up to 1 ns and a resolution of ± 28.5 ps at 23C. The proton and heavy ion tests were conducted at the China Institute of Atomic Energy. The energies of protons are 70, 80, and 100 MeV. Heavy ions used in the test include Cl, Ti, and Ge. The fluence of heavy ions is 1×10cm, and the fluence of protons is 2.46×10 cm. SET cross section. The LET of a high-energy proton is too small to cause the SETs by direct ionization. Instead, high-energy protons induce the SETs by creating secondary particles through proton/material nuclear interactions. These secondary particles have much higher LET than the incident protons. The SET cross-section is defined as the detected SETs divided by the particle fluence. From Figure 1(a), the cross-section of highenergy proton induced the SETs is relatively small, from 5×10 cm to about 1×10 cm, which confirms that the SETs induced by the protons are attributed to the secondary particles rather than the protons themselves. From Figure 1(b), we

Radiation Study of SEE in ASIC Fabricated in 0.18μm Technology

The research on the radiation effects of ASIC has been the hot point in the field of the international aerospace devices. This paper developed a test system for the single event effects (SEEs), which was applied to test the radiation effects of some domestic ASIC chips. Based on the result, SEEs under different work conditions: high temperature, normal temperature, low voltage, normal voltage were analyzed. Thus the voltage and temperature effects on SEE can be studied. The test showed that the increasing temperature and decreasing voltage could affect SEEs, meanwhile the sensibility of the ASIC circuit to SEE will be enhanced. The high temperature and low voltage is the worst work condition to the ASIC circuit, and there is no latch-up on the work condition of high temperature and high voltage.

New Latch-Up Model for Deep Sub-micron Integrated Circuits

This paper mainly simulated the single event latch-up (SEL) for the CMOS inverter under the 0.18um technology. The SEL of integrated circuit (IC) was also analyzed in detail. The result showed that the parasitic lateral transistors NPN and PNP of NMOS and PMOS play a role in the SEL happening process. The changes of the drain voltage and the drain current and the functional failure of the circuit were also explained in further. Therefore the new SEL model could be established.

Analysis of the New Latchup Model for Deep Sub-micron Integrated Circuits

The paper simulated the SEL happening process of the CMOS inverter fabricated the 0.18um technology. The results show that the intrinsic parasitic lateral NPN (QN) and PNP (QP) transistor of the NMOS and PMOS in the CMOS inverter, which could result in the changes of the voltage and the current of the drain when the SEL happening, can delay latch up occurring time and reduce the latch up current. The origin model was improved based on the simulated results. The result studying the improved latch up model shows that the smaller ratios of the internal parasitic resistors between RW1 and RW2 or RS1 and RS2 could lead to smaller latch up current and delay more time for the latch up occurrence.The paper simulated the SEL happening process of the CMOS inverter fabricated the 0.18um technology. The results show that the intrinsic parasitic lateral NPN (QN) and PNP (QP) transistor of the NMOS and PMOS in the CMOS inverter, which could result in the changes of the voltage and the current of the drain when the SEL happening, can delay latch up occurring time and reduce the latch up current. The origin model was improved based on the simulated results. The result studying the improved latch up model shows that the smaller ratios of the internal parasitic resistors between RW1 and RW2 or RS1 and RS2 could lead to smaller latch up current and delay more time for the latch up occurrence.