Hongge Li

A low-noise integrated bioamplifier with active DC offset suppression

This paper describes a novel low-power, low-noise amplifier for neural recording applications. The bioamplifier achieves the best power-size tradeoff compared to the previous design. By means of a new active feedback configuration, the DC offset is rejected without the large capacitors. An active differentiator with an amplifier in the feedback path places a high-pass cutting frequency in the transfer function. The midband gain consists of the passive components, and is insensitive to the mismatch of process. The bioamplifier has been implemented in the Chartered 0.35-μm 2P4M CMOS process and occupies 0.022mm2 of chip area. The current consumption of amplifier is 2μA at ±1.5V supply. The bioamplifier achieves a midband gain of 46dB and a −3dB bandwidth from 13Hz to 8.9kHz. The input-referred noise is 5.7μVrms corresponding to an NEF of 3.1.

Cell array reconfigurable architecture for high-efficiency AES system

Abstract This paper present the issue of standard security algorithms with reconfigurable cell array architecture. The reconfigurable Advanced Encryption Standard (AES) architecture is proposed for high performance information security applications. The reconfiguration architecture based on cell array processing elements is connected to each other through the interconnect routing and the switchbox. AES operations are performed on a two-dimensional array using four rows and four columns for the encryption with 128-bit Key length. The Key expansion unit is set the flexible architecture with 128-, 196- and 256-bit cipher Key length. The reconfigurable Key generator further increases the AES hardware flexibility. The operation of SubBytes and XOR is implemented with internal cell of array, but ShiftRow and MixColumns must depend on co-ordination between cells of array. Sixteen free cells of array are connected using the switchbox to operate the encryption of AES algorithm. The on-line fault detection based on parity code is designed to check fault cell. The cell array AES architecture is simulated with Verilog HDL. The prototype system of reconfigurable cell array AES is verified using a field programmable gate array (FPGA). The experiment results show that the proposed method achieves a high-efficiency, low-hardware overhead and high reliability for the information security.

Types of serrations in Al-Li single crystals

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The cryogenic properties of Al-Li single crystals

Abstracts are not published in this journal