Hongshan Nie

High Accuracy Biological Impedance Measurement System Design and Calibration

The application of biological impedance measurement demands for high-accuracy and fast-speed. A novel measurement system for biological impedance measurement based on automatic balancing bridge is proposed. Besides the improvement on accuracy introduced by bridge method, the utilization of the Least Mean Square (LMS) method guarantees the measurement speed. We designed calibration method to eliminate the error inducted by the practical circuit. The test results reveal the in-phase and quadrature component measurement errors of the proposed system with calibration are respectively lower than 2 percent and 3.2 percent in the range of 1KHz to 1MHz. The system has advantages of high-accuracy and fast-speed which fit for biological impedance measurement applications.

High Speed Real-Time Data Acquisition System Based on Solid-State Storage Technique

This paper presented a high speed data acquisition system for real-time appLication. The hardware of system mainly consists of data acquisition, distribution and storage section. A 3Gsps ultra high-speed ADC is appLied in acquisition section. In distribution section, the original data stream will be distributed into four streams. Each data stream will be stored into one soLid-state storage card which is composed of NAND flash array. In aspect of software, implementation methods of DDR3-based FIFO and NAND flash controller were introduced in detail. System evaluation results show that system achieved high bandwidth (up to 3.0GB/s) and good SNR (up to 45dB).

A Group-Based Hybrid Wear-Leveling Algorithm for Flash Memory Storage Systems

Wear-leveling algorithm is required in most flash memory controllers to prolong the lifetime of flash memory by distributing the erase operations evenly across the whole flash memory. This paper proposes a group based wear-leveling algorithm which can dramatically reduce the RAM space required by wear-leveling algorithm while maintaining the wear-leveling performance. We adopt random wear-leveling policy which requires very little RAM space inside a group to make the data in the group move around and the wear in the group respectively even. And a threshold controlled static wear-leveling policy is adopted among different groups to make the average wear of different groups even. A series of trace-driven simulations show that our group based algorithm consumes only 78% of RAM space compare with previous group-based wear-leveling algorithm which require complex data structure, while maintaining nearly the same wear-leveling performance.

Parallel Parity Scheme for Reliable Solid-State Disks

Recently, solid-state disks (SSDs) have been extensively applied in many fields. However, with increasing storage density in SSDs, a liability problem has emerged as a significant restriction. A parallel parity scheme is proposed in this paper. This scheme employs a mapping table based on a physical block address and a partial delayed parity update. Experimental results demonstrate the proposed scheme not only improves the reliability of SSDs, but also enhances their performance.

An Efficient Flash-Based Remote Sense Image Storage Approach for Fast Access Geographic Information System

Fast accessing of geographic remote sense image (GRSI) in geographic information system has been a different problem in the region of remote sense information processing for years. This paper proposes a efficient way called IBSA (Image blocking storage approach) for GRSI based on the flash storage technology which is a hot research topic in data storage field. IBSA exploits a blocking approach which adequately considers the characteristics of the GRSI, such as its huge size, its partial accessing feature and its strong requirement for high speed. Simulating result shows that, the proposed approach has a good performance on the access efficiency and can be widely used in the future work of geographic information system study.

High Accuracy Dynamic Adjusting Voltage Source for Cell Impedance Tomography Application

This paper presented a high accuracy voltage source with current limiting function. A high-speed (250 MHz), high-resolution (16 bit) dual DAC is used for generating stimulate voltage by DDS technique. The amplitude of source could be adjusted by wide bandwidth, low noise variable gain amplifiers from -11 to +51 dB. The 4-Opamp architecture is applied to realize a high gain, high-accuracy variable gain instrument amplifier circuit for tiny current sensing. By using analog comparator to convert over-current time into length of digital pulse, the FPGA could monitor the amplitude of current in real-time. Evaluation results show that system has good SFDR performance and fast response speed. With the advantages of accuracy and bandwidth, it is suitable for cell impedance tomography application.