Hongsik Park

High-density integration of carbon nanotubes via chemical self-assembly

Carbon nanotubes have potential in the development of high-speed and power-efficient logic applications. However, for such technologies to be viable, a high density of semiconducting nanotubes must be placed at precise locations on a substrate. Here, we show that ion-exchange chemistry can be used to fabricate arrays of individually positioned carbon nanotubes with a density as high as 1xa0×xa010(9)xa0cm(-2)-two orders of magnitude higher than previous reports. With this approach, we assembled a high density of carbon-nanotube transistors in a conventional semiconductor fabrication line and then electrically tested more than 10,000 devices in a single chip. The ability to characterize such large distributions of nanotube devices is crucial for analysing transistor performance, yield and semiconducting nanotube purity.

Toward High-Performance Digital Logic Technology with Carbon Nanotubes

The slow-down in traditional silicon complementary metal-oxide-semiconductor (CMOS) scaling (Moores law) has created an opportunity for a disruptive innovation to bring the semiconductor industry into a postsilicon era. Due to their ultrathin body and ballistic transport, carbon nanotubes (CNTs) have the intrinsic transport and scaling properties to usher in this new era. The remaining challenges are largely materials-related and include obtaining purity levels suitable for logic technology, placement of CNTs at very tight (∼5 nm) pitch to allow for density scaling and source/drain contact scaling. This review examines the potential performance advantages of a CNT-based computing technology, outlines the remaining challenges, and describes the recent progress on these fronts. Although overcoming these issues will be challenging and will require a large, sustained effort from both industry and academia, the recent progress in the field is a cause for optimism that these materials can have an impact on future technologies.

Principle of direct van der Waals epitaxy of single-crystalline films on epitaxial graphene

There are numerous studies on the growth of planar films on sp(2)-bonded two-dimensional (2D) layered materials. However, it has been challenging to grow single-crystalline films on 2D materials due to the extremely low surface energy. Recently, buffer-assisted growth of crystalline films on 2D layered materials has been introduced, but the crystalline quality is not comparable with the films grown on sp(3)-bonded three-dimensional materials. Here we demonstrate direct van der Waals epitaxy of high-quality single-crystalline GaN films on epitaxial graphene with low defectivity and surface roughness comparable with that grown on conventional SiC or sapphire substrates. The GaN film is released and transferred onto arbitrary substrates. The post-released graphene/SiC substrate is reused for multiple growth and transfer cycles of GaN films. We demonstrate fully functional blue light-emitting diodes (LEDs) by growing LED stacks on reused graphene/SiC substrates followed by transfer onto plastic tapes.

Layer-Resolved Graphene Transfer via Engineered Strain Layers

Monolayer Graphene via Two Transfers Oriented monolayers of graphene containing some bilayer regions can be formed on silicon carbide crystal surfaces, but, to be cost effective, the graphene needs to be exfoliated and transferred to other substrates so that the silicon carbide crystal can be reused. Kim et al. (p. 833, published online 31 October) used a nickel film grown to a thickness designed to impart a particular surface stress as a “handle” to exfoliate the graphene layer for transfer to a silica substrate. An additional gold layer was then used to remove the excess monolayer from the bilayer regions to create a monolayer suitable for electronics applications. A two-step exfoliation process allows multiple transfers of oriented monolayer graphene from a silicon carbide surface. The performance of optimized graphene devices is ultimately determined by the quality of the graphene itself. Graphene grown on copper foils is often wrinkled, and the orientation of the graphene cannot be controlled. Graphene grown on SiC(0001) via the decomposition of the surface has a single orientation, but its thickness cannot be easily limited to one layer. We describe a method in which a graphene film of one or two monolayers grown on SiC is exfoliated via the stress induced with a Ni film and transferred to another substrate. The excess graphene is selectively removed with a second exfoliation process with a Au film, resulting in a monolayer graphene film that is continuous and single-oriented.

Carbon nanotube thin film transistors on flexible substrates

Carbon nanotube thin film transistors (CNT-TFTs) are fabricated on flexible substrates using purified, surfactant-based CNT suspensions, with >95% semiconducting CNT fraction. The TFTs are made up of local bottom-gated structures with aluminum oxide as the gate dielectric. The devices exhibit high ON current densities (0.1 μA/μm) and on-off ratios (∼105) with mobility values ranging from 10-35 cm2/Vs. A detailed numerical model is used to understand the TFT performance and its dependence on device parameters such as TFT channel length, CNT density, and purity.

9.4% Efficient Amorphous Silicon Solar Cell on High Aspect-Ratio Glass Microcones

High aspect-ratio three-dimensional (3D) a-Si:H solar cells have been fabricated to enhance a light absorption path while maintaining a short carrier collection length. Substantial efficiency enhancement in 3D solar cells was achieved due to the boost in JSC with no degradation of FF which is comparable to FF obtained from 2D solar cells.

Physically unclonable cryptographic primitives using self-assembled carbon nanotubes.

Information security underpins many aspects of modern society. However, silicon chips are vulnerable to hazards such as counterfeiting, tampering and information leakage through side-channel attacks (for example, by measuring power consumption, timing or electromagnetic radiation). Single-walled carbon nanotubes are a potential replacement for silicon as the channel material of transistors due to their superb electrical properties and intrinsic ultrathin body, but problems such as limited semiconducting purity and non-ideal assembly still need to be addressed before they can deliver high-performance electronics. Here, we show that by using these inherent imperfections, an unclonable electronic random structure can be constructed at low cost from carbon nanotubes. The nanotubes are self-assembled into patterned HfO2 trenches using ion-exchange chemistry, and the width of the trench is optimized to maximize the randomness of the nanotube placement. With this approach, two-dimensional (2D) random bit arrays are created that can offer ternary-bit architecture by determining the connection yield and switching type of the nanotube devices. As a result, our cryptographic keys provide a significantly higher level of security than conventional binary-bit architecture with the same key size.

Variability and reliability analysis in self-assembled multichannel carbon nanotube field-effect transistors

Carbon nanotubes (CNTs) have been widely studied as a channel material of scaled transistors for high-speed and low-power logic applications. In order to have sufficient drive current, it is widely assumed that CNT-based logic devices will have multiple CNTs in each channel. Understanding the effects of the number of CNTs on device performance can aid in the design of CNT field-effect transistors (CNTFETs). We have fabricated multi-CNT-channel CNTFETs with an 80-nm channel length using precise self-assembly methods. We describe compact statistical models and Monte Carlo simulations to analyze failure probability and the variability of the on-state current and threshold voltage. The results show that multichannel CNTFETs are more resilient to process variation and random environmental fluctuations than single-CNT devices.

Carbon nanotube complementary logic based on Erbium contacts and self-assembled high purity solution tubes

Complementary logic gates based on chemically assisted directed assembly of solution carbon nanotubes with a high semiconducting purity (~91%) are demonstrated. Air stable, high quality carbon nanotube NFETs have been fabricated with low work function Erbium contacts, enabling an inverter gain of > 7 from transistors with 50 nm channel lengths. The substantial device yields of both NFET (~31%) and PFET (~44%) on the same chip allow us to construct and test a large number of CNT complementary logic gates for the first time. > 11% inverter yield from over 400 circuits tested along with fully functional NAND2 gates show promise of our fabrication scheme. This study points out several key directions for further yield enhancement, in which increasing the successful rate of CNT deposition into the trench plays a major role.

Evaluation of metal–nanowire electrical contacts by measuring contact end resistance

It is known, but often unappreciated, that the performance of nanowire (NW)-based electrical devices can be significantly affected by electrical contacts between electrodes and NWs, sometimes to the extent that it is really the contacts that determine the performance. To correctly understand and design NW device operation, it is thus important to carefully measure the contact resistance and evaluate the contact parameters, specific contact resistance and transfer length. A four-terminal pattern or a transmission line model (TLM) pattern has been widely used to measure contact resistance of NW devices and the TLM has been typically used to extract contact parameters of NW devices. However, the conventional method assumes that the electrical properties of semiconducting NW regions covered by a metal are not changed after electrode formation. In this study, we report that the conventional methods for contact evaluation can give rise to considerable errors because of an altered property of the NW under the electrodes. We demonstrate that more correct contact resistance can be measured from the TLM pattern rather than the four-terminal pattern and correct contact parameters including the effects of changed NW properties under electrodes can be evaluated by using the contact end resistance measurement method.