Hongyi Lu

A dynamically-allocated virtual channel architecture with congestion awareness for on-chip routers

In this paper, the dynamically-allocated virtual channels (VCs) architecture with congestion awareness is introduced. All the buffers are shared among VCs whose structure varies with traffic condition. In low rate, this structure extends VC depth for continual transfers to reduce packet latencies. In high rate, it dispenses many VCs and avoids congestion situations to improve the throughput. We modify the VC controller and VC allocation modules, while designing simple congestion avoidance logic. The experiment shows that the proposed routers outperform conventional ones under different traffic patterns. They provide 8.3% throughput increase and 19.6% latency decrease while saving 27.4% of area and 28.6% of power.

A 6.35Mbps 1024-bit RSA crypto coprocessor in a 0.18um CMOS technology

In this paper a RSA crypto coprocessor that is fabricated using a 0.18mum CMOS technology is presented. This processor combines a new version of high radix Montgomery multiplication algorithm with a super-pipeline design. With this algorithm, modular exponentiation can be decomposed into a series of primitive operation (PO) matrixes. All the POs are scheduled on the pipeline by employing column-sharing strategy, and inside the PO all the partial results are compressed first by Wallace tree to assure only one carry propagation in the critical path. With these optimizations, a decryption rate of 6.35 Mbps can be achieved for 1024-bit RSA

TengYue-1: A High Performance Embedded SoC

TengYue-1 is a microprocessor subsystem for embedded applications. Its heart is a 32-bit RISC microprocessor based on an instruction set architecture (ISA) designed by us. Through a WISHBONE compatible on-chip bus, the microprocessor, a universal memory controller, a LCD controller and other peripheral I/Os formed the SOC. TengYue-1 has been implemented and verified in SMIC 0.18um CMOS technology, and the maximum clock frequency is 300MHz@1.8V. This paper presents the design and implementation of TengYue-1. We used 9 ARM benchmarks to evaluate the performance of the microprocessor and the results showed that it met our goal. We also found a simple solution to the memory access conflict problem caused by the microprocessor core and the LCD controller.

A Low-Latency Virtual-Channel Router with Optimized Pipeline Stages for On-Chip Network

Network-on-Chip (NoC), as the next generation interconnection technology on chip, facilitates a high-bandwidth communication and improves the performance of communication observably. Since the NoC performance closely relies on the intra-router latency, a low-latency virtual-channel router with optimized pipeline stage is proposed in this study. By utilizing look-ahead routing algorithm and speculation switch allocation strategy, the pipeline depth is shortened to two stages. To further shorten the critical path of designs, this study also proposes a three-way parallel arbitration mechanism when designing low-latency virtual-channel allocator and speculative switch allocator. The experiment results show the allocators present the good scalability to different virtual channel and physical port numbers and the pipeline stage delay is reduced by 33% compared with the traditional one. Then, the proposed router can provide throughput increase and latency decrease with 19 and 25%, respectively, compared to the traditional router.

Designing power analysis resistant and high performance block cipher coprocessor using WDDL and wave-pipelining

Novel design method and design flow of block cipher coprocessor is presented based on the WDDL (Wave Dynamic Differential Logic) and Wave-Pipelining techniques. This design flow utilized the current commercially available EDA (Electronic Design Automatic) tools to a large degree. The WDDL and wave-pipelining based coprocessor not only resists power analysis, but also achieves high performance and low power consumption in nature. According to the design flow, this paper implements a DES coprocessor. The simulation results show that the novel design method does achieve high performance, low power consumption and power analysis resistant ability at the cost of chip area.