Hoongjoo Lee

Selective emitter using a screen printed etch barrier in crystalline silicon solar cell

The low level doping of a selective emitter by etch back is an easy and low cost process to obtain a better blue response from a solar cell. This work suggests that the contact resistance of the selective emitter can be controlled by wet etching with the commercial acid barrier paste that is commonly applied in screen printing. Wet etching conditions such as acid barrier curing time, etchant concentration, and etching time have been optimized for the process, which is controllable as well as fast. The acid barrier formed by screen printing was etched with HF and HNO3 (1:200) solution for 15 s, resulting in high sheet contact resistance of 90 Ω/sq. Doping concentrations of the electrode contact portion were 2 × 1021 cm−3 in the low sheet resistance (Rs) region and 7 × 1019 cm−3 in the high Rs region. Solar cells of 12.5 × 12.5 cm2 in dimensions with a wet etch back selective emitter Jsc of 37 mAcm−2, open circuit voltage (Voc) of 638.3 mV and efficiency of 18.13% were fabricated. The result showed an improvement of about 13 mV on Voc compared to those of the reference solar cell fabricated with the reactive-ion etching back selective emitter and with Jsc of 36.90 mAcm−2, Voc of 625.7 mV, and efficiency of 17.60%.

Analysis of Resistance and Surface Recombination Velocities by Contact Coverage for Optimizing Electrical Loss in c-Si Local Back Contact.

Recently, the importance of solar cell research has emerged due to emerging social issues such as environmental pollution problems and rising oil prices. Accordingly, each company is studying to make solar cell of high efficiency. In order to fabricate high-efficiency solar cells, the two major techniques have to be applied on the rear. One is complete passivation of the surface using a thermal oxide and the other one is the part that comes in contact with the electrode doped partially LBSF (Local BSF) formation. In this paper, LBC technology which is usually applied for high efficiency crystalline silicon solar cell, applied to mass productive solar cell to achieve high open circuit voltage and short circuit current with low surface recombination from rear side. Thermal SiO2/SiN(x) double layer which has superior thermal stability is formed on rear surface as passivation layer, then 1% of the whole rear surface area is locally contacted with aluminum. Finally, the cell has been fired at high temperature and the cell process has complete. The fabricated LBC cells conversion efficiency was 18.0% with 625 mV of open-circuit voltage (V(oc)), 37.58 mA/cm2 of current density (J(sc)), 76.3% of fillfactor (FF) at 5% contact coverage, respectively.

Correction simulation for simultaneous suppression of overlaps and side-lobes in attenuated PSM lithography

Problems of overlap errors and side-lobe printing by the design rule reduction in the lithography process using attenuated phase-shifting masks (attPSM) have been serious. Overlap errors and side-lobes can be simultaneously solved by the rule-based correction using scattering bars with the rules extracted from test patterns. Process parameters affecting the attPSM lithography simulation have been determined by the fitting method to the process data. Overlap errors have been solved applying the correction rules to the metal patterns overlapped with contact/via. Moreover, the optimal insertion rule of the scattering bars has made it possible to suppress the side-lobes and to get additional pattern fidelity at the same time.

Circuit model parameter generation with TCAD simulation

In the case of the Hash memory, various kinds of transistors and the wide range of operation voltage are necessary to achieve the read/write operations. Therefore, the characteristics of transistors are measured in the silicon for the circuit design, and the test vehicle run must he processed. In this study, an efficient design flow is suggested using TCAD tools. The test vehicle is replaced with well-calibrated TCAD simulation. First, the calibration methodology is introduced and tested for flash memory device. The calibration errors are less than 5% of a full chip operation, which is accepted by the designers. The results of the calibration were used to predict I-V curves and model parameter of the various transistors for the design of flash device.