Hossein Fariborzi

Demonstration of integrated micro-electro-mechanical switch circuits for VLSI applications

Due to transistor leakage, CMOS circuits have a well-defined lower limit on their achievable energy efficiency [1]. Once this limit is reached, power-constrained applications will face a cap on their maximum throughput independent of their level of parallelism. Avoiding this roadblock requires an alternate switching device with steeper sub-threshold slope—i.e., lower VDD/Ion for the same Ion/Ioff [2]. One promising class of such devices with nearly ideal Ion/Ioff characteristics are electro-statically actuated micro-electro-mechanical (MEM) switches [6]. Although mechanical movement makes MEM circuit delay significantly larger than that of CMOS, we have recently shown that with optimized circuit topologies MEM switches may potentially enable ∼10x lower energy over CMOS at up to ∼100MHz frequencies [3].

EAMTR: energy aware multi-tree routing for wireless sensor networks

IEEE 802.15.4 is the prevailing standard for low-rate wireless personal area networks. It specifies the physical layer and medium access control sub-layer. Some emerging standards such as ZigBee define the network layer on top of these lower levels to support routing and multi-hop communication. Tree routing is a favourable basis for ZigBee routing because of its simplicity and limited use of resources. However, in data collection systems that are based on spanning trees rooted at a sink node, non-optimal route selection, congestion and uneven distribution of traffic in tree routing can adversely contribute to network performance and lifetime. The imbalance in workload can result in hotspot problems and early energy depletion of specific nodes that are normally the crucial routers of the network. The authors propose a novel light-weight routing protocol, energy aware multi-tree routing (EAMTR) protocol, to balance the workload of data gathering and alleviate the hotspot and single points of failure problems for high-density sink-type networks. In this scheme, multiple trees are formed in the initialisation phase and according to network traffic, each node selects the least congested route to the root node. The results of simulation and performance evaluation of EAMTR show significant improvement in network lifetime and traffic distribution.

Design and demonstration of micro-electro-mechanical relay multipliers

This paper describes the micro-architecture and circuit techniques for building multipliers with micro-electromechanical (MEM) relays. By optimizing the circuits and micro-architecture to suit relay device characteristics, the performance of the relay based multiplier is improved by a factor of ∼8× over any known static CMOS-style implementation, and ∼4× over CMOS pass-gate equivalent implementations. A 16-bit relay multiplier is shown to offer ∼10× lower energy per operation at sub-10 MOPS throughputs when compared to an optimized CMOS multiplier at an equivalent 90 nm technology node. To demonstrate the viability of this technology, we experimentally demonstrate the operation of the primary multiplier building block: a full (7:3) compressor, built with 98 MEM-relays, which is the largest working MEM-relay circuit reported to date.

Analysis and demonstration of MEM-relay power gating

This paper shows that due to their negligibly low leakage, in certain applications, chips utilizing power gates built even with todays relatively large, high-voltage micro-electro-mechanical (MEM) relays can achieve lower total energy than those built with CMOS transistors. A simple analysis provides design guidelines for off-time and savings estimates as a function of technology parameters, and quantifies the further benefits of scaled relay designs. Finally, we demonstrate a relay chip successfully power-gating a CMOS chip, and show a relay-based timer suitable for self-timed operation.

Relays do not leak: CMOS does

This paper describes the micro-architectural and circuit design techniques for building complex VLSI circuits with microelectromechanical (MEM) relays and presents experimental results to demonstrate the viability of this technology. By tailoring the circuits and micro-architecture to the relay device characteristics, the performance of the relay-based multiplier is improved by an order of magnitude over any known static CMOS style implementation, and by ~4x over CMOS pass-gate equivalent implementations. A 16-bit relay multiplier is shown to offer -10x lower energy per operation at sub-10 MOPS throughputs when compared to an optimized CMOS multiplier at an equivalent 90 nm technology node. The functionality of the primary multiplier building block, a full (7:3) compressor built with 46 scaled MEM-relays, which is the largest working MEM-relay circuit reported to date, is also demonstrated.

Microelectromechanical resonator based digital logic elements

Micro/nano-electromechanical resonator based mechanical computing has recently attracted significant attention. However, its full realization has been hindered by the difficulty in realizing complex combinational logics, in which the logic function is constructed by cascading multiple smaller logic blocks. In this work we report an alternative approach for implementation of digital logic core elements, multiplexer and demultiplexer, which can be used to realize combinational logic circuits by suitable concatenation. Toward this, shallow arch shaped microresonators are electrically connected and their resonance frequencies are tuned based on an electrothermal frequency modulation scheme. This study demonstrates that by reconfiguring the same basic building block, the arch microresonator, complex logic circuits can be realized.

Improved circuit model for all-spin logic

Spintronic devices are prime candidates for Beyond CMOS era due to their potential for low power consumption and high density computation and storage. All-spin logic (ASL) is among the most promising spintronic logic switches. Previous attempts to model ASL in the linear and diffusive regime either neglect the dynamic characteristics of the transport or do not provide a scalable and robust platform for full micromagnetic simulations and inclusion of other effects like spin Hall effect (SHE) and spin-orbit torque (SOT). In this paper, and based on a finite difference scheme, we propose an improved self-consisting magnetization dynamics/time-dependent carrier transport model that captures the main characteristics of ASL devices.

Improved StrongARM latch comparator: Design, analysis and performance evaluation

This paper presents an improved StrongARM latch comparator, designed and simulated in 90nm and 32nm CMOS technologies. The proposed design provides an improvement of 7% in energy efficiency, 14% in speed and an average reduction of 41% in the clock feedthrough, compared to the conventional design. The new architecture also minimizes the area by reducing the required transistors needed for the enhanced performance.

Axially Modulated Clamped-Guided Arch Resonator for Memory and Logic Applications

We experimentally demonstrate memory and logic devices based on an axially modulated clamped-guided arch resonator. The device are electrostatically actuated and capacitively sensed, while the resonance frequency modulation is achieved through an axial electrostatic force from the guided side of the clamped guided arch microbeam. We present two case studies: first, a dynamic memory based on the nonlinear frequency response of the resonator, and second, a reprogrammable two-input logic gate based on the linear frequency modulation of the resonator. These devices show energy cost per memory/logic operation in pJ, are fully compatible with CMOS fabrication processes, have the potential for on-chip system integration, and operate at room temperature.

A numerical analysis and experimental demonstration of a low degradation conductive bridge resistive memory device

This study investigates a low degradation metal-ion conductive bridge RAM (CBRAM) structure. The structure is based on placing a diffusion blocking layer (DBL) between the devices top electrode (TE) and the resistive switching layer (RSL), unlike conventional CBRAMs, where the TE serves as a supply reservoir for metallic species diffusing into the RSL to form a conductive filament (CF) and is kept in direct contact with the RSL. The properties of a conventional CBRAM structure (Cu/HfO2/TiN), having a Cu TE, 10 nm HfO2 RSL, and a TiN bottom electrode, are compared with a 2 nm TaN DBL incorporating structure (Cu/TaN/HfO2/TiN) for 103 programming and erase simulation cycles. The low and high resistive state values for each cycle are calculated and the analysis reveals that adding the DBL yields lower degradation. In addition, the 2D distribution plots of oxygen vacancies, O ions, and Cu species within the RSL indicate that oxidation occurring in the DBL-RSL interface results in the formation of a sub-stoich...