Howard G. Sachs

The Clipper processor: instruction set architecture and implementation

Intergraphs CLIPPER microprocessor is a high performance, three chip module that implements a new instruction set architecture designed for convenient programmability, broad functionality, and easy future expansion.

An architecture for high instruction level parallelism

High instruction level parallelism (ILP) can only be achieved when data flow and control flow constraints have been removed or reduced. Data flow constraints, not inherent in the original code, arise from lack of sufficient resources for initiation and execution of multiple instructions concurrently. Control flow, problems are caused by branches which force unpredictable changes in the sequential order of code execution. Removing these obstacles allows for the formation of larger basic blocks, resulting in higher ILP. The dataflow problems are reduced by increasing the number of functional units, registers, condition bits, by pipelining the functional units, and using nonblocking caches. The control flow problem is reduced by using techniques such as conditional execution, speculative execution, and software pipelining, leveraging hardware support. Thus, for high ILP, the processor architecture should include a very closely tied hardware and compiler architectures. An architecture that supports the above features, Software Scheduled SuperScalar, is presented in this paper.<<ETX>>

Method and apparatus for translating virtual addresses in a data processing system having multiple instruction pipelines and separate TLB's for each pipeline

A computing system has multiple instruction pipelines, wherein one or more pipelines require translating virtual addresses to real addresses. A TLB is provided for each pipeline requiring address translation services, and an adress translator is provided for each such pipeline for translating a virtual address recieved from its associated pipeline into corresponding real addresses. Each address translator comprises a translation buffer accessing circuit for accessing the TLB, a translation indicating circuit for indicating whether translation data for the virtual address is stored in the translation buffer, and an update control circuit for activating the direct address translation circuit when the translation data for the virtual address is not stored in the TLB. The update control circuit also stores the translation data retrieved from the main memory into the TLB. If it is desired to have the same translation information available for all the pipelines in a group, then the update control circuit also updates all the other TLBs in the group.

Future directions in CLIPPER processors

After a brief survey of CLIPPER RISC (reduced instruction set computer) processor generations to date, the authors look ahead to what can be expected from CLIPPER in the 1991-5 time frame. They examine in some depth what they regard as the key trends over the next decade, both in microprocessor architectures and implementation technologies, and they indicate how they expect the CLIPPER to relate to these emerging directions for microprocessors. Their conclusions is that the last six years have demonstrated the validity of the balanced path pursued to date with the CLIPPER, and they do not expect the next decade to call for a radical break with the past.<<ETX>>

Design and implementation trade-offs in the Clipper C400 architecture

A description is given of the C400, the first complete redesign of the Clipper reduced instruction-set computing architecture since its introduction in 1985. The C400 delivers three times the performance of the C300, yet retains full-code compatibility with earlier Clippers. The C400 combines two architectural approaches to attain its performance goals. The first approach, superscalar operation, allows the processor to begin the execution of more than one instruction during each clock cycle. The C400, which is moderately superscalar, can dispatch two instructions per clock cycle. The C400 also embodies the design concept of superpipelining, an approach that emphasizes high clock rates and deep execution pipelines in attaining high computational performance. The discussion covers the programming model, early hardware implementations, the C400 project goals and approaches, C400 performance, the integer unit design, the load/store pipeline, the floating-point unit design, the superscalar/superpipelined architecture, circuit design, and the advantages of the multichip implementation.<<ETX>>

Hot Chips 18

Over its 18-year history, the Hot Chips conference has become a leading forum for the latest computing, communications, and networking chips. The conference covers a variety of technical details about these chips, including technology, fundamental algorithms, packaging techniques, architecture, and circuit details. This issue features six of the best presentations from Hot Chips 18, expanded to full articles. Topics include multiprocessor/multicore systems, embedded processing, and low-power processing.