Howard L. Levy
Sun Microsystems
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Publication
Featured researches published by Howard L. Levy.
custom integrated circuits conference | 2004
Jinuk Luke Shin; Bruce Petrick; Howard L. Levy; Jinseung Son; Mandeep Singh; Vikas Mathur; Jung-Cheng Yeh; Heesung Choi; Vishal Gupta; Tom Ziaja; Ana Sonia Leon
Dual on-chip 512 kB unified second level (L2) caches for an UltraSparc processor are implemented using 0.13 /spl mu/m technology. Each 512 kB unit is implemented using 34 million transistors to achieve 1.4 GHz and 2.6 W at 13 V and 85 C. This fully integrated subsystem is composed of data and tag SRAMs along with datapaths, controller and test engines. The unit achieves one of the shortest on-chip L2 cache latencies reported for 64b microprocessors, with a data latency of only 4 cycles including ECC correction for 128-bit data. The design solutions to build this integrated short latency L2 cache are discussed.
Archive | 2003
Nadeem N. Eleyan; Harsh Dev Sharma; Howard L. Levy; Hong S. Kim
Archive | 2002
Nadeem N. Eleyan; Howard L. Levy; Jeffrey Y. Su
Archive | 2003
Howard L. Levy; Nadeem N. Eleyan; Harsh D. Sharma; Hong Kim
Archive | 2003
Nadeem N. Eleyan; Howard L. Levy; Jeffrey Y. Su
international solid-state circuits conference | 2004
Toshinari Takayanagi; Jinuk Luke Shin; Bruce Petrick; Jeffrey Y. Su; Howard L. Levy; Ha Pham; Jinseung Son; Nathan Moon; Dina Bistry; Umesh Nair; Mandeep Singh; Vikas Mathur; Ana Sonia Leon
Archive | 2002
Nadeem N. Eleyan; Howard L. Levy; Jeffrey Y. Su
Archive | 2003
Nadeem N. Eleyan; Howard L. Levy; Jeffrey Y. Su
Archive | 2006
Dennis Wendell; Howard L. Levy; Jinuk Luke Shin
Archive | 2002
Harsh D. Sharma; Howard L. Levy; Hong Kim; Nadeem N. Eleyan
