Hsi-Chuan Chen

Process to reduce defect formation occurring during shallow trench isolation formation

Growth enhancement of hemispherical grain silicon on a doped polysilicon storage node capacitor structure, for dynamic random access memory applications

Method of selective growth of a hemispherical grain silicon layer on the outer sides of a crown shaped DRAM capacitor structure

Resolution of hemispherical grained silicon peeling and row-disturb problems for dynamic random access memory, stacked capacitor structures

Method of manufacturing hemispherical grained polysilicon with improved adhesion and reduced capacitance depletion

Method for fabricating a stacked, or crown shaped, capacitor structure

One step in situ doped amorphous silicon layers used for selective hemispherical grain silicon formation for crown shaped capacitor applications

Process for integrating hemispherical grain silicon and a nitride-oxide capacitor dielectric layer for a dynamic random access memory capacitor structure

In situ, one step, formation of selective hemispherical grain silicon layer, and a nitride-oxide dielectric capacitor layer, for a DRAM application

Method to decrease capacitance depletion, for a DRAM capacitor, via selective deposition of a doped polysilicon layer on a selectively formed hemispherical grain silicon layer