Hsiao-Cheng Chiang

Abnormal hump in capacitance-voltage measurements induced by ultraviolet light in a-IGZO thin-film transistors

This work demonstrates the generation of abnormal capacitance for amorphous indium-gallium-zinc oxide (a-InGaZnO4) thin-film transistors after being subjected to negative bias stress under ultraviolet light illumination stress (NBIS). At various operation frequencies, there are two-step tendencies in their capacitance-voltage curves. When gate bias is smaller than threshold voltage, the measured capacitance is dominated by interface defects. Conversely, the measured capacitance is dominated by oxygen vacancies when gate bias is larger than threshold voltage. The impact of these interface defects and oxygen vacancies on capacitance-voltage curves is verified by TCAD simulation software.

Investigation of a Hump Phenomenon in Back-Channel-Etched Amorphous In-Ga-Zn-O Thin-Film Transistors Under Negative Bias Stress

The hump phenomenon along with a negative shift of threshold voltage emerging in the transfer characteristics of amorphous InGaZnO thin-film transistors under negative bias stress was investigated. Higher measurement temperature and larger bias voltage can induce more and faster hole injection, thus leading to the increased parasitic ON-state current and more negative shift of the threshold voltage. Nevertheless, the parasitic current is independent of the channel width, illustrating that the parasitic channel originates from the hole trapping near the IGZO edges along the channel length. Integrated Systems Engineering Technology Computer-aided Design simulation confirms that the electric field near the IGZO edge is relatively dense, and the direction is more conducive for the holes in IGZO to inject into passivation (PV), to gate insulator (GI), or at PV/GI interface.

Gate Insulator Morphology-Dependent Reliability in Organic Thin-Film Transistors

In this letter, we investigated the gate insulator morphology affecting on the electric characteristic variation for organic thin-film transistors (OTFTs). From the transfer characteristics, there is a result with leakage current when the gate voltage is lower than the threshold voltage, which is due to the gate insulator thickness variation. Furthermore, regardless of whether the OTFT is operated under positive or negative bias stress, the more severe degradation happened in the hump region of transfer characteristics. Because a thinner gate insulator causes a high electric field, more charges are trapped in a gate dielectric stack.

Surface Engineering of Polycrystalline Silicon for Long-Term Mechanical Stress Endurance Enhancement in Flexible Low-Temperature Poly-Si Thin-Film Transistors

The surface morphology in polycrystalline silicon (poly-Si) film is an issue regardless of whether conventional excimer laser annealing (ELA) or the newer metal-induced lateral crystallization (MILC) process is used. This paper investigates the stress distribution while undergoing long-term mechanical stress and the influence of stress on electrical characteristics. Our simulated results show that the nonuniform stress in the gate insulator is more pronounced near the polysilicon/gate insulator edge and at the two sides of the polysilicon protrusion. This stress results in defects in the gate insulator and leads to a nonuniform degradation phenomenon, which affects both the performance and the reliability in thin-film transistors (TFTs). The degree of degradation is similar regardless of bending axis (channel-length axis, channel-width axis) or bending type (compression, tension), which means that the degradation is dominated by the protrusion effects. Furthermore, by utilizing long-term electrical bias stresses after undergoing long-tern bending stress, it is apparent that the carrier injection is severe in the subchannel region, which confirms that the influence of protrusions is crucial. To eliminate the influence of surface morphology in poly-Si, three kinds of laser energy density were used during crystallization to control the protrusion height. The device with the lowest protrusions demonstrates the smallest degradation after undergoing long-term bending.

Effect of SiO 2 Buffer Layer Thickness on Performance and Reliability of Flexible Polycrystalline Silicon TFTs Fabricated on Polyimide

This letter investigates flexible polycrystalline silicon thin film transistor performance variation due to different buffer layer thicknesses. In flexible electronics, thermal expansion stress during device fabrication is inevitable. A thicker SiO2 buffer demonstrates better endurance to thermal expansion stress from the polyimide substrate during device annealing. However, if the SiO2 buffer thickness is above a critical point, its weak heat dissipation capability causes the optimal ELA crystallization condition to shift. A thermal expansion stress simulation and TEM photos were utilized to verify performance variation. Furthermore, a similar trend was observed in electrical characteristics after negative bias temperature instability.

Floating top gate-induced output enhancement of a-InGaZnO thin film transistors under single gate operations

This work compares dual gate and single gate a-InGaZnO thin film transistor devices under single gate operations. In both devices, an abnormal drain current increase in the dual gate structures was observed. The results of structural geometry experiments, Technology Computer-Aided Design, and theoretical calculations matching the experimental results provide evidence for a larger voltage potential distribution located near the top gate even when the top gate is floating. Since an additional voltage is formed near the top gate, a better gate control capability will lead to more inverted carriers. Therefore, these dual gate structures have a larger drain current than does the single gate. Finally, both positive bias stress and negative bias illumination stress in both structures are discussed. The results of positive bias stress have shown good quality of the gate insulator layer and negative bias illumination stress was discussed to confirm the coupled voltage.This work compares dual gate and single gate a-InGaZnO thin film transistor devices under single gate operations. In both devices, an abnormal drain current increase in the dual gate structures was observed. The results of structural geometry experiments, Technology Computer-Aided Design, and theoretical calculations matching the experimental results provide evidence for a larger voltage potential distribution located near the top gate even when the top gate is floating. Since an additional voltage is formed near the top gate, a better gate control capability will lead to more inverted carriers. Therefore, these dual gate structures have a larger drain current than does the single gate. Finally, both positive bias stress and negative bias illumination stress in both structures are discussed. The results of positive bias stress have shown good quality of the gate insulator layer and negative bias illumination stress was discussed to confirm the coupled voltage.

Investigating degradation behaviors induced by mobile Cu ions under high temperature negative bias stress in a-InGaZnO thin film transistors

This letter investigates the effect of negative bias temperature stress (NBTS) on amorphous InGaZnO4 thin film transistors with copper electrodes. After 2000 s of NBTS, an abnormal subthreshold swing and on-current (Ion) degradation is observed. The recovery of the Id-Vg curve after either annealing or positive bias temperature stress suggests that there are some native mobile copper ions in the active layer. Both the existence of copper and the degradation mechanism can be confirmed by AC stress with different frequencies and by transmission electron microscope energy-dispersive X-ray spectroscopy analysis.

Investigation of an anomalous hump phenomenon in via-type amorphous In-Ga-Zn-O thin-film transistors under positive bias temperature stress

Amorphous InGaZnO thin film transistors (a-IGZO TFTs) with an etching-stop layer (ESL) exhibit an anomalous negative shift of threshold voltage (Vth) under positive bias temperature stress. TFTs with wider and shorter channels show a clear hump phenomenon, resulting from the existence of both main channels and parasitic channels. The electrons trapped in the gate insulator are responsible for the positive shift in the main channel characteristics. The electrons trapped near the IGZO edges and the holes injected into the ESL layer above InGaZnO (IGZO) jointly determine the shift of the parasitic TFT performance.

H2O adsorption on amorphous In-Ga-Zn-O thin-film transistors under negative bias stress

Amorphous In-Ga-Zn-O thin-film transistors on flexible substrates were prepared to investigate H2O adsorption under negative bias stress (NBS). Shorter channel lengths induce a more seriously deteriorated NBS stability due to the stronger electric field near the source or drain electrode. With increasing channel width, the NBS instability increases to a peak and then slightly decreases. Integrated Systems Engineering Technology Computer-aided Design (ISE-TCAD) simulation confirms that the electric field near the source/drain in the etch-stop layer is relatively dense, especially near the channel edges. The electric field direction is also confirmed to have significant effects on the H2O adsorption process.

Identical off-state current raise induced by photo-induced schottky barrier lowering in a-InGaZnO 4 thin film transistors

This work studies the mechanism of identical photo-induced leakage current in a-InGaZnO4 thin film transistors during reverse gate voltage sweep. There is the identical off-state current with the reverse sweep under UV light irradiation, and the photocurrent for UV light exposure region near the source electrode is more significant than that near the drain electrode, which is different from photocurrent mechanism of low temperature polysilicon TFTs. This is because the photo-generated electrons increase the carrier concentration in a-InGaZnO4 bulk, causing the reduced depletion width of the active layer. Therefore, the back channel of active layer is out of gate control.