Hsie-Chia Chang

An LDPC Decoder Chip Based on Self-Routing Network for IEEE 802.16e Applications

An LDPC decoder chip fully compliant to IEEE 802.16e applications is presented. Since the parity check matrix can be decomposed into sub-matrices which are either a zero-matrix or a cyclic shifted matrix, a phase-overlapping message passing scheme is applied to update messages immediately, leading to enhance decoding throughput. With only one shifter-based permutation structure, a self-routing switch network is proposed to merge 19 different sub-matrix sizes as defined in IEEE 802.16e and enable parallel message to be routed without congestion. Fabricated in the 90 nm 1P9M CMOS process, this chip achieves 105 Mb/s at 20 iterations while decoding the rate-5/6 2304-bit code at 150 MHz operation frequency. To meet the maximum data rate in IEEE 802.16e, this chip operates at 109 MHz frequency and dissipates 186 mW at 1.0 V supply.

A Reed-Solomon product-code (RS-PC) decoder chip for DVD applications

The digital versatile disk (DVD), an emerging standard of optical storage, provides a higher capacity than audio CD, CD-ROM or video CD (VCD). To mitigate the errors introduced during manufacturing or by user damage, a Reed-Solomon Product-Code (RS-PC) is used in DVD for error correction. For this application, the authors present an RS-PC decoder chip with a dual-frame-buffer architecture. The decoder chip contains two frame buffer controllers that interface with two off-chip frame buffers, a (182,172) row RS decoder and a (208,192) column RS decoder. The chip uses a cell library in a 0.6 /spl mu/m SPDM CMOS process. The 99-pin chip is packaged in a 100 LDCQFP package, where 48 pins are for frame buffer interface and can be eliminated with embedded frame buffers. The row and column RS decoders work at 33 MHz with a 3 V supply. The RS-PC decoder is currently limited in speed by the off-chip frame buffer to about 18 MHz. The power dissipation is 102 mW at 33 MHz.

Design of a power-reduction Viterbi decoder for WLAN applications

In this paper, a 64-state four-bit soft-decision Viterbi decoder with power saving mechanism for high speed wireless local area network applications is presented. Based on path merging and prediction techniques, a survivor memory unit with hierarchical memory design is proposed to reduce memory access operations. It is found that more than 70% memory access can be reduced by taking advantage of locality. Moreover, a low complexity compare-select-add unit is also presented, leading to save 15% area and 14.3% power dissipation as compared to conventional add-compare-select design. A test chip has been designed and implemented in 0.18-/spl mu/m standard CMOS process. The test results show that 30/spl sim/40% power dissipation can be reduced, and the power efficiency reaches 0.75 mW per Mb/s at 6 Mb/s and 1.26 mW per Mb/s at 54 Mb/s as specified in IEEE 802.11a.

A 3.33Gb/s (1200,720) low-density parity check code decoder

In this paper, a (1200,720) LDPC decoder based on an irregular parity check matrix is presented. For achieving higher chip density and less critical path delay, the proposed architecture features a data reordering such that only one specific data bus exists between message memories and computational units. Moreover, the LDPC decoder can also process two different codewords concurrently to increase throughput and datapath efficiency. After chip implementation, a 3.33Gb/s data rate is achieved with 8 decoding iterations in the 21.23mm/sup 2/ 0.18/spl mu/m silicon area. The other 0.13/spl mu/m chip with the 10.24mm/sup 2/ core can further reach a 5.92Gb/s data rate under 1.02V supply.

Efficient Power-Analysis-Resistant Dual-Field Elliptic Curve Cryptographic Processor Using Heterogeneous Dual-Processing-Element Architecture

Elliptic curve cryptography (ECC) for portable applications is in high demand to ensure secure information exchange over wireless channels. Because of the high computational complexity of ECC functions, dedicated hardware architecture is essential to provide sufficient ECC performance. Besides, crypto-ICs are vulnerable to side-channel information leakage because the private key can be revealed via power-analysis attacks. In this paper, a new heterogeneous dual-processing-element (dual-PE) architecture and a priority-oriented scheduling of right-to-left double-and-add-always EC scalar multiplication (ECSM) with randomized processing technique are proposed to achieve a power-analysis-resistant dual-field ECC (DF-ECC) processor. For this dual-PE design, a memory hierarchy with local memory synchronization scheme is also exploited to improve data bandwidth. Fabricated in a 90-nm CMOS technology, a 0.4- mm2 160-b DF-ECC chip can achieve 0.34/0.29 ms 11.7/9.3 μJ for one GF(p)/GF(2m) ECSM. Compared to other related works, our approach is advantageous not only in hardware efficiency but also in protection against power-analysis attacks.

Reconfigurable Turbo Decoder With Parallel Architecture for 3GPP LTE System

This brief presents a parallel architecture for the turbo decoder using the quadratic permutation polynomial interleaver. The supported block size ranges from 40 to 6144 with an increment of 8, and thus, it includes 188 sizes in the 3rd Generation Partnership Project Long Term Evolution standard. The proposed design can allow one, two, four, or eight soft-in/soft-out decoders to process each block with configurable iterations. To support all data transmissions in the parallel design, a multistage network with low complexity is also utilized. Moreover, a robust path metric initialization is given to improve the performance loss in small blocks and high parallelism. After fabrication in the 90-nm process, the 2.1-mm2 chip can achieve 130 Mb/s with 219 mW for the size-6144 block and eight iterations.

A 45nm 6b/cell charge-trapping flash memory using LDPC-based ECC and drift-immune soft-sensing engine

To satisfy the demand of higher storage density, storing multiple-bits-per-cell technique is widely adopted. As presented in [1], a 4b/cell Flash memory by using error-detection (ED) scheme stores 2b data on two sides of a memory cell individually. Since the noise margin becomes smaller, the distribution drifts due to program disturb, data retention and temperature variation will cause higher raw bit-error-rate (RBER) if the sensing level (voltage) are not adjusted accordingly. The ED scheme can detect the drift direction by counting and storing the number of cells (Ni) with threshold voltage (VTH) below the ith sensing level (VREF i). A simple example with page size 1KB is demonstrated in Fig. 12.7.1. During a read operation, the number of cells (Ni, measured) whose VTH below VREF i is counted and compared to Ni. The ED scheme can find out a sub-optimal sensing level when Ni, measured and Ni is close enough. In this paper, a production 16Gb 45nm 4b/cell ONO-based charge-trapping (CT) Flash memory is demonstrated to achieve 6b/cell capability. Since the adjacent distributions for 6b/cell are much closer to each other, even a BCH code with ED scheme fails to correct all the patterns. However, by using a new 1-3-3 mapping and LDPC codes with a developed drift-immune soft-sensing (DI-SS) engine, the 45nm 4b/cell CT Flash memory is boosted to 6b/cell. The data flow of programming data is also shown in Fig. 12.7.1.

A 5.79-Gb/s Energy-Efficient Multirate LDPC Codec Chip for IEEE 802.15.3c Applications

An LDPC codec chip supporting four code rates of IEEE 802.15.3c applications is presented. After utilizing row-based layered scheduling, the normalized min-sum (NMS) algorithm can reduce half of the iteration number while maintaining similar performance. According to the unique code structure of the parity-check matrix, a reconfigurable 8/16/32-input sorter is designed to deal with LDPC codes in four different code rates. Both sorter input reallocation and pre-coded routing switch are proposed to alleviate routing complexity, leading to 64% input reduction of multiplexers. In addition, an adder-accumulator-shift register (AASR) circuit is proposed for the LDPC encoder to reduce hardware complexity. After implemented in 65-nm 1P10M CMOS process, the proposed LDPC decoder chip can achieve maximum 5.79-Gb/s throughput with the hardware efficiency of 3.7 Gb/s/mm2 and energy efficiency of 62.4 pJ/b, respectively.

A 480Mb/s LDPC-COFDM-based UWB baseband transceiver

A low-density parity-check (LDPC) coded OFDM-based UWB baseband transceiver features a semi-regular LDPC CODEC, a parallel pipelined FFT, and a division-free channel equalizer. The chip is implemented in a standard 0.18 /spl mu/m CMOS process and achieves a 480Mbit/s data rate with an energy consumption of 1.2nJ/b.

Design of a Multimode QC-LDPC Decoder Based on Shift-Routing Network

A reconfigurable message-passing network is proposed to facilitate message transportation in decoding multimode quasi-cyclic low-density parity-check (QC-LDPC) codes. By exploiting the shift-routing network (SRN) features, the decoding messages are routed in parallel to fully support those specific 19 and 3 submatrix sizes defined in IEEE 802.16e and IEEE 802.11n applications with less hardware complexity. A 6.22- mm2 QC-LDPC decoder with SRN is implemented in a 90-nm 1-Poly 9-Metal (1P9M) CMOS process. Postlayout simulation results show that the operation frequency can achieve 300 MHz, which is sufficient to process the 212-Mb/s 2304-bit and 178-Mb/s 1944-bit codeword streams for IEEE 802.16e and IEEE 802.11n systems, respectively.