Hsin-Chia Lu

60-GHz Four-Element Phased-Array Transmit/Receive System-in-Package Using Phase Compensation Techniques in 65-nm Flip-Chip CMOS Process

AThe 60-GHz four-element phased-array transmit/receive (TX/RX) system-in-package antenna modules with phase-compensated techniques in 65-nm CMOS technology are presented. The design is based on the all-RF architecture with 4-bit RF switched LC phase shifters, phase compensated variable gain amplifier (VGA), 4:1 Wilkinson power combining/dividing network, variable-gain low-noise amplifier, power amplifier, 6-bit unary digital-to-analog converter, bias circuit, electrostatic discharge protection, and digital control interface (DCI). The 2 × 2 TX/RX phased arrays have been packaged with four antennas in low-temperature co-fired ceramic modules through flip-chip bonding and underfill process, and phased-array beam steering have been demonstrated. The entire beam-steering functions are digitally controllable, and individual registers are integrated at each front-end to enable beam steering through the DCI. The four-element TX array results in an output of 5 dBm per channel. The four-element RX array results in an average gain of 25 dB per channel. The four-element array consumes 400 mW in TX and 180 mW in RX and occupies an area of 3.74 mm2 in the TX integrated circuit (IC) and 4.18 mm2 in the RX IC. The beam-steering measurement results show acceptable agreement of the synthesized and measured array pattern.

Port reduction methods for scattering matrix measurement of an n-port network

The port reduction method (PRM) is a method to acquire the scattering matrix of an n-port network from the scattering matrix measured at a reduced port order by terminating certain ports. This then relaxes the instrumentation requirement and calibration procedure. As the port order is reduced to two, the scattering matrix of an n-port network can be obtained from the measurement using a conventional two-port vector network analyzer. In this paper, we describe two novel PRMs, which can reduce the order of measured ports to two. The experimental results show good accuracy. These two PRMs can provide a simpler calibration procedure and instrumentation than those directly using an n-port network analyzer. In addition, they give more accurate results than those measured by a two-port network analyzer with the assumption of using ideal terminators.

Multiport scattering matrix measurement using a reduced-port network analyzer

A novel method to acquire the scattering matrix of an n-port network from the measurements using a reduced-port network analyzer is developed. This method can obtain the scattering matrix of a nonreciprocal or reciprocal n-port network with the use of a three-port or two-port network analyzer. The formulation of this method considers the imperfection of terminators used in the measurement, and only two of the terminators are required to be known. Experimental results of a four-port microstrip circuit show the good accuracy using the developed method.

MMICs in the millimeter-wave regime

On the basis of the current status of silicon based MMICs, it is possible to implement millimeter-wave SOC in silicon-based technologies that include the antenna, a medium-power amplifier, a transceiver, an LO (frequency synthesizer), and baseband circuits in a single chip. With certain interconnection schemes, such as flip-chip, to connect the chip to the substrate, it is also possible to integrate the best possible chips for a millimeter-wave communication system. Currently, CMOS is the best choice for the baseband circuits, while GaAs and InP MMICs can provide the best noise/power performance in the transceiver. High-efficiency antennas can be implemented directly on the packaging substrate. The SIP approach has the optimal combinations of the components for the best performance in a particular system. For example, a system in a package including CMOS baseband circuits, GaAs/InP-based transceiver, high-efficiency antenna, and high-power amplifier can achieve the best system characteristics. As we have discussed, the scope of SOC can be expanded along with more advanced MMIC fabrication technology and design techniques.

Flip-Chip-Assembled

In this paper, W-band flip-chip-assembled CMOS chip modules with transition compensation are presented, a three-stage amplifier, a balanced amplifier, and a down-converted Gilbert-cell subharmonic mixer are included in the chip set. The flip-chip process on ceramic integrated passive devices (CIPD) with a bump size of 30 μm × 30 μm × 27 m is developed for millimeter-wave applications. Without the flip-chip transition compensation, the frequency of the return loss of each chip is shifted, which deviates from the bare die measurement results. By applying the compensation network in the transition, the dips of the return loss are tuned back closer to the bare die measurement results. Moreover, a W-band amplifier flip-chip-assembled with a CPW-fed Yagi-Uda antenna on a CIPD and a W-band flip-chip-assembled receiver are presented for SiP integration. The effect of dicing edge variation is also included in the flip-chip model to achieve reasonable agreement between simulated and measured scattering parameters. To the best of our knowledge, this is the first demonstration of a CMOS chip set with flip-chip interconnects in the -band for a system-in-package.

W

Two V-band low-noise amplifiers (LNAs) with excellent linearity and noise figure (NF) using 90-nm CMOS technology are demonstrated in this paper, employing parasitic-insensitive linearization topologies, i.e., cascode and common source, for comparative purposes. To improve the linearity without deteriorating the NF, the 54-69-GHz cascode LNA is linearized by the body-biased post-distortion, and the 58-65-GHz common-source LNA is linearized by the distributed derivative superposition. Using these parasitic-insensitive linearization methods at millimeter-wave frequency, the cascode LNA can achieve an IIP3 of 11 dBm and an NF of 3.78 dB at 68.5 GHz with a gain of 13.2 dB and 14.4-mW dc power. The common-source LNA has an IIP3 of 0 dBm and an NF of 4.1 dB at 64.5 GHz with a gain of 11.3 dB and 10.8-mW dc power. To the best of our knowledge, the proposed cascode LNA has up to 11-dBm IIP3 performance and the highest figure-of-merit of 156.2, among all reported V-band LNAs.

-Band CMOS Chip Modules on Ceramic Integrated Passive Device With Transition Compensation for Millimeter-Wave System-in-Package Integration

In this paper, a fully system-in-package (SiP) integrated V-band Butler matrix beam-switching transmitter (TX) is presented. The CMOS chips from differential process technologies are assembled on a low-temperature co-fired ceramic (LTCC) substrate carrier by flip-chip interconnects. The vertically embedded folded monopole antenna is designed and integrated into the LTCC. The array consisting of four identical monopole antennas and a Butler matrix for beam switching is realized on the LTCC for loss reduction. Four switched main beams are measured and agree well with simulation. This beam-forming TX shows the potential of the low-cost millimeter-wave SiP with CMOS chips.

Parasitic-Insensitive Linearization Methods for 60-GHz 90-nm CMOS LNAs

In RF/microwave circuit design, inductor design is one of the most difficult and time-consuming tasks due to the tedious trial-and-error optimization process to achieve the target specifications such as inductance, quality factor and occupied space. This paper brings forward a fast spiral inductor synthesis method, which automatically generates physical layout of inductors according to electrical specifications. By fusion of substrate-aware partial element equivalent circuit (PEEC) model with nonlinear optimization engine, our modeling and synthesis strategies have been verified with industrial field solver and measurement results. Our calculation results got less than 7% error for inductance and less than 9% for quality factor as compared to the results from full-wave electromagnetic simulation software. This can provide a fast and good initial inductor design for designer.

A Fully SiP Integrated

Mutual inductance between coupled inductors can provide large equivalent series inductance required by filter design. As mutual inductance is dependent on the distance between coupled metal lines within coupled inductors, mutual inductance in traditional straight line coupled inductors (SLCI) is susceptible to layer-to-layer misalignment during fabrication if two coupled lines are located at different substrate layers. Misalignment-tolerant coupled inductors (MaTCI) are proposed to alleviate the effect of misalignment on mutual inductance. Circuit model is also proposed to describe their mechanism. Their performance is verified and compared with traditional SLCI using coupled inductors based transmission zero circuits and bandpass filters. Measurement results of three samples of a transmission zero circuit based on proposed MaTCI show only 0.56% frequency variation at 1.9 GHz, while traditional SLCI give about 3.2% variation from samples at the same low temperature cofired ceramic substrate. Measured results of three samples of a bandpass filter using MaTCI also show more stable performance at transmission zero frequency, insertion loss and passband bandwidth as compared with the filter using traditional SLCI. Electromagnetic simulation also shows similar performance improvement for MaTCI under misalignment. The same concept is also applied to helical inductor and two misalignment tolerant helical inductors are proposed. Simulation results show that they are more stable than the traditional stacked helical inductor.

V

This paper presents the equivalent circuit of radiating longitudinal slots in substrate integrated waveguide (SIW). The simulated results using a MoM simulator are compared with measured results. They are shown in good agreement. These equivalent circuit is later used in the design of an array antenna using these slots as radiating elements.